Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.

Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.

Oscillator circuit uses a comparator, and controls charge-discharge of Miller capacitance between gate and drain of a MOSFET serving as an amplifier of the comparator gain unit and gate capacitance of the MOSFET, and enables comparator output to follow a high-frequency control signal that is input externally. An oscillator circuit uses a comparator CMP having differential and gain units. This oscillator circuit includes: a charge-discharge controller to control charge-discharge of Miller capacitance between gate and drain of a MOSFET and gate capacitance of the MOSFET; and an output controller to control output of the gain unit. Output controller includes: an inverter to connect to an input of the differential unit and receive a control signal input; a logic circuit to receive output of the inverter and output of the gain unit as an input; a transistor; and a capacitor to connect to input and output of the logic circuit.

An operation signal generating unit 11 and a reset unit 12 are included in a first circuit unit 10 that operates based on a first power supply voltage V1 and an output operation of a second power supply voltage B2 is stopped by outputting a reset signal Sr from the reset unit 12 to a regulator 20 in accordance with an operation signal Si of the operation signal generating unit 11. Hence, unlike a conventional technique, a large transistor for cutting off a power supply line is unnecessary, and therefore a device size can be reduced.

An operation signal generating unit 11 and a reset unit 12 are included in a first circuit unit 10 that operates based on a first power supply voltage V1 and an output operation of a second power supply voltage B2 is stopped by outputting a reset signal Sr from the reset unit 12 to a regulator 20 in accordance with an operation signal Si of the operation signal generating unit 11. Hence, unlike a conventional technique, a large transistor for cutting off a power supply line is unnecessary, and therefore a device size can be reduced.

Provided is an oscillator arranged to output an oscillation signal of an oscillation frequency having an increasing and decreasing component that increases and decreases in one period, and an offset component for each period.

Provided is an oscillator arranged to output an oscillation signal of an oscillation frequency having an increasing and decreasing component that increases and decreases in one period, and an offset component for each period.

Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.

Provided is an electronic device including a ramp signal generation circuit configured to generate a ramp signal having a second slope that is greater by a first level than a first slope which corresponds to an analog gain, and a slope correction circuit configured to correct the second slope of the ramp signal by the first level to obtain the first slope.

A latch circuit includes a switch circuit, an input circuit, and an output circuit. The switch circuit is coupled between a first power node and a second power node, and includes a non-inverting output node and an inverting output node. The input circuit couples with the non-inverting output node and the inverting output node, and conducts the non-inverting output node with the second power node according to a clock signal and a data signal. The output circuit couples with the non-inverting output node, the inverting output node, the first power node, and the second power node. The output circuit conducts the non-inverting output node with the first power node according to the clock signal and the data signal. When the data signal is switched, the switch circuit sets a conductive path from the first power node to the second power node as an open circuit.