The present disclosure relates to a device for generating a clock signal including a first photoresistor coupling a capacitive output node to a node receiving a first potential. A second photoresistor couples the capacitive node to a node receiving a second potential. The first and second photoresistors receive the same optical pulses of a mode-locked laser at instants in time offset by a first delay.

The present disclosure relates to a device for generating a clock signal including a first photoresistor coupling a capacitive output node to a node receiving a first potential. A second photoresistor couples the capacitive node to a node receiving a second potential. The first and second photoresistors receive the same optical pulses of a mode-locked laser at instants in time offset by a first delay.

A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in addition to the first die, a Through Substrate Via insert is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. A second die is mounted on the back side of the substrate, with contacts on the second die in electrical connection with the TSV insert's contacts on the back side of the substrate. On the front side of the substrate, a lateral connecting device is mounted which interconnects the TSV insert's contacts on the front side of the substrate to contacts on the front side of the first die. The lateral connecting device and the TSV insert thereby effectively interconnect the contacts on the first and second dies. In another aspect, the lateral connecting device is mounted on a redistribution layer on the front side of the substrate, as it is known from FO-WLP technology.

A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in addition to the first die, a Through Substrate Via insert is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. A second die is mounted on the back side of the substrate, with contacts on the second die in electrical connection with the TSV insert's contacts on the back side of the substrate. On the front side of the substrate, a lateral connecting device is mounted which interconnects the TSV insert's contacts on the front side of the substrate to contacts on the front side of the first die. The lateral connecting device and the TSV insert thereby effectively interconnect the contacts on the first and second dies. In another aspect, the lateral connecting device is mounted on a redistribution layer on the front side of the substrate, as it is known from FO-WLP technology.

An exponentially-scaling switched impedance circuit includes: two or more impedance scaling circuits, wherein each impedance scaling circuit comprises: an input port; an output port; and a switched impedance circuit connected in parallel to the output port. Each impedance scaling circuit is configured to provide an effective impedance at the input port corresponding to a scaled-down version of the exponentially-scaling switched impedance circuit. The two or more impedance scaling circuits are connected in a cascade such that an input of an impedance scaling circuit is connected to an output of a previous impedance scaling circuit and/or an output of the impedance scaling circuit is connected to an input of a next impedance scaling circuit.

An exponentially-scaling switched impedance circuit includes: two or more impedance scaling circuits, wherein each impedance scaling circuit comprises: an input port; an output port; and a switched impedance circuit connected in parallel to the output port. Each impedance scaling circuit is configured to provide an effective impedance at the input port corresponding to a scaled-down version of the exponentially-scaling switched impedance circuit. The two or more impedance scaling circuits are connected in a cascade such that an input of an impedance scaling circuit is connected to an output of a previous impedance scaling circuit and/or an output of the impedance scaling circuit is connected to an input of a next impedance scaling circuit.

A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in addition to the first die, a Through Substrate Via insert is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. A second die is mounted on the back side of the substrate, with contacts on the second die in electrical connection with the TSV insert's contacts on the back side of the substrate. On the front side of the substrate, a lateral connecting device is mounted which interconnects the TSV insert's contacts on the front side of the substrate to contacts on the front side of the first die. The lateral connecting device and the TSV insert thereby effectively interconnect the contacts on the first and second dies. In another aspect, the lateral connecting device is mounted on a redistribution layer on the front side of the substrate, as it is known from FO-WLP technology.

A package including a first die embedded in a reconstructed wafer obtainable by the known FO-WLP or eWLB technologies is disclosed. In one aspect and in addition to the first die, a Through Substrate Via insert is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias interconnecting contacts on the front and back sides of the insert. A second die is mounted on the back side of the substrate, with contacts on the second die in electrical connection with the TSV insert's contacts on the back side of the substrate. On the front side of the substrate, a lateral connecting device is mounted which interconnects the TSV insert's contacts on the front side of the substrate to contacts on the front side of the first die. The lateral connecting device and the TSV insert thereby effectively interconnect the contacts on the first and second dies. In another aspect, the lateral connecting device is mounted on a redistribution layer on the front side of the substrate, as it is known from FO-WLP technology.

The present invention relates to a method for manufacturing a multilayer thin FPCB, and the method for manufacturing a multilayer thin FPCB according to the present invention relates to a method for manufacturing an FPCB (Flexible Printed Circuit Board) comprising coating metal nanoparticles on a first flexible substrate of a thin film; applying a laser to the metal nanoparticles to sinter the metal nanoparticles and pattern them; cleaning the metal nanoparticles unsintered; laminating a second flexible substrate of a thin film on the first flexible substrate in which a pattern is formed; forming a via hole on the second flexible substrate using a laser; coating metal nanoparticles on the second flexible substrate; applying a laser to the metal nanoparticles to sinter the metal nanoparticles and pattern them; and cleaning the metal nanoparticles unsintered.

Various RF plasma systems are disclosed that do not require a matching network. In some embodiments, the RF plasma system includes an energy storage capacitor; a switching circuit coupled with the energy storage capacitor, the switching circuit producing a plurality of pulses with a pulse amplitude and a pulse frequency, the pulse amplitude being greater than 100 volts; a resonant circuit coupled with the switching circuit. In some embodiments, the resonant circuit includes: a transformer having a primary side and a secondary side; and at least one of a capacitor, an inductor, and a resistor. In some embodiments, the resonant circuit having a resonant frequency substantially equal to the pulse frequency, and the resonant circuit increases the pulse amplitude to a voltage greater than 2 kV.