In one form, a multiphase controller for controlling a plurality of phases using a corresponding plurality of phase controllers includes a plurality of inputs, each for receiving a respective current monitor signal, an averaging circuit for generating an averaged signal representative of an average of current monitor signals received from said plurality of inputs, wherein each phase controller generates an error voltage in response to said averaged signal and said respective current monitor signal, controls a drive signal in response to said error voltage and a control voltage, and provides a digital signal representative of a difference between said error voltage and said control voltage. The multiphase controller provides an adjustment signal representative of said digital signal divided by a corresponding output current for each phase controller, and said adjustment signal adjusts a corresponding error voltage.

In one form, a multiphase controller for controlling a plurality of phases using a corresponding plurality of phase controllers includes a plurality of inputs, each for receiving a respective current monitor signal, an averaging circuit for generating an averaged signal representative of an average of current monitor signals received from said plurality of inputs, wherein each phase controller generates an error voltage in response to said averaged signal and said respective current monitor signal, controls a drive signal in response to said error voltage and a control voltage, and provides a digital signal representative of a difference between said error voltage and said control voltage. The multiphase controller provides an adjustment signal representative of said digital signal divided by a corresponding output current for each phase controller, and said adjustment signal adjusts a corresponding error voltage.

A power line communication driver circuit drives a power communication line with a power line communication signal that supplies both power and control data to a plurality of electronic devices. The power line communication driver circuit includes a ramp generator that receives an input signal encoding digital data and generates a ramp signal that switches between a low non-zero ramp voltage and a high ramp voltage to encode the digital data. The power line communication driver circuit furthermore includes a buffer circuit that receives and buffers the ramp signal to generate the power line communication signal. In one application, the power line communication driver circuit may drive a group of zone integrated circuits that include driver circuits for driving respective LED zones of a display device.

A power line communication driver circuit drives a power communication line with a power line communication signal that supplies both power and control data to a plurality of electronic devices. The power line communication driver circuit includes a ramp generator that receives an input signal encoding digital data and generates a ramp signal that switches between a low non-zero ramp voltage and a high ramp voltage to encode the digital data. The power line communication driver circuit furthermore includes a buffer circuit that receives and buffers the ramp signal to generate the power line communication signal. In one application, the power line communication driver circuit may drive a group of zone integrated circuits that include driver circuits for driving respective LED zones of a display device.

A controller includes a ramp circuit and control logic. The ramp circuit includes: ramp generation circuitry having a first control input and a first current output; ramp adjustment circuitry having a second control input and a second current output; current scaling circuitry having a first current input, a current sense output and an offset current output, the first current input coupled to the first and second current outputs; and ramp completion circuitry having a current sense input and a completion output, the current sense input coupled to the current sense output. The control logic has a third control input and first and second control outputs. The third control input is coupled to the completion output. The first control output is coupled to the first control input. The second control output is coupled to the second control input.

A controller includes a ramp circuit and control logic. The ramp circuit includes: ramp generation circuitry having a first control input and a first current output; ramp adjustment circuitry having a second control input and a second current output; current scaling circuitry having a first current input, a current sense output and an offset current output, the first current input coupled to the first and second current outputs; and ramp completion circuitry having a current sense input and a completion output, the current sense input coupled to the current sense output. The control logic has a third control input and first and second control outputs. The third control input is coupled to the completion output. The first control output is coupled to the first control input. The second control output is coupled to the second control input.

A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.

A device includes a first ramp generator having a first ramp generator output configured to provide a first ramp, a second ramp generator having a second ramp generator output configured to provide a second ramp, and a third ramp generator having a third ramp generator output configured to provide a third ramp. The first ramp is a sawtooth voltage waveform having a first common mode voltage and a first peak-to-peak voltage. The second ramp is a sawtooth voltage waveform having a second common mode voltage and a second peak-to-peak voltage. The third ramp is a sawtooth voltage waveform having a third common mode voltage and a third peak-to-peak voltage. A frequency of the second ramp is approximately equal to a frequency of the third ramp, and the frequency of the third ramp is approximately double a frequency of the first ramp.

A duty point detection circuit receiving an input signal and generating an output signal includes a charge pump receiving the input signal and the output signal and generating a comparison target signal from the input signal and the output signal, a magnitude of the comparison target signal being determined based on a first duty ratio of the input signal and a second duty ratio of the output signal, a comparator receiving a reference signal and the comparison target signal, and comparing the reference signal and the comparison target signal to generate a comparison result signal, and a control circuit receiving the input signal and the comparison result signal and adjusting the second duty ratio of the output signal to a constant duty ratio in successive cycle periods of the input signal.

A duty point detection circuit receiving an input signal and generating an output signal includes a charge pump receiving the input signal and the output signal and generating a comparison target signal from the input signal and the output signal, a magnitude of the comparison target signal being determined based on a first duty ratio of the input signal and a second duty ratio of the output signal, a comparator receiving a reference signal and the comparison target signal, and comparing the reference signal and the comparison target signal to generate a comparison result signal, and a control circuit receiving the input signal and the comparison result signal and adjusting the second duty ratio of the output signal to a constant duty ratio in successive cycle periods of the input signal.