A phase correcting circuit includes a delay circuit that receives an input clock signal and delays the input clock signal as much as a first delay time to output an output clock signal to a 0-th node, a first fine tuning circuit, and a second fine tuning circuit. The first fine tuning circuit includes a first terminal connected with the 0-th node, a second terminal receiving a first control signal, and a third terminal, and the second fine tuning circuit includes a fourth terminal connected with the third terminal, a fifth terminal receiving a second control signal, and a sixth terminal connected with a load capacitor. In response to the first control signal, the output clock signal may be further delayed as much as a second delay time shorter than the first delay time. In response to the second control signal, the output clock signal may be advanced as much as a third delay time shorter than the first delay time.

Programming time delay data in an oversampled sensor includes determining whether to enter Programming Mode based on a value of a system parameter received by the oversampled sensor. Programming Mode is entered when the value of the system parameter corresponds to Programming Mode. The time delay data is programmed in the oversampled sensor during Programming Mode. The oversampled sensor uses the time delay data to time delay its output in an oversampled domain. Programming Mode is exited after a predetermined time has expired relative to when Programming Mode was entered. The system parameter can be a frequency of a sampling clock signal.

Detecting voltage-based attacks on an integrated circuit (IC) is difficult in the presence of clock jitter. Propagating signals can exhibit a total delay that is due to a delay component resulting from a voltage-based attack and a delay characteristic resulting from clock fluctuation. Voltage-variation detection circuitry includes first and second voltage-dependent circuits and a voltage analysis circuit. The voltage-dependent circuits produce first and second signals that are indicative of a voltage level responsive to a clock signal and based on different first and second voltage sensitivities. The voltage analysis circuit generates a voltage alert signal based on the first and second signals. A combined signal neutralizes the delay characteristic in the first and second signals, but the delay component due to the voltage variation can be at least partially maintained. Thus, a voltage-based attack is detectable in the presence of clock fluctuation by using two voltage-dependent circuits.

Aspects of the technology described herein relate to ultrasound device circuitry as may form part of a single substrate ultrasound device having integrated ultrasonic transducers. The ultrasound device circuitry may facilitate the generation of ultrasound waveforms in a manner that is power- and data-efficient.

A low-latency signaling link retimer generates an output signal transmission synchronously with respect to a core clock signal alternately selected from two or more plesiochronous or mesochronous clock sources with switchover between or among the core-clock sources executed without shrinking, extending or otherwise disrupting the edge-to-edge core clock period or clock duty cycle.

A “frequency shifter” is a clock synthesis system, that includes either a multiplexer or a multi-modulus divider (MMD), a fractional frequency divider, a tunable delay element, a sawtooth signal generator, in addition to other synchronization and control circuits. The generated sawtooth signal is used to control the delay of the tunable delay element, which in turn is used to adjust the phase of the signal generated by either M-to-1 multiplexer or the MMD, reducing its timing errors, and improving the spectral purity of the generated clock signal.

An improved circuit or method generates first and second initial pulses that do not overlap. First and second drive pulses are generated based on the first and second initial pulses, respectively. A first transistor is turned on with the first drive pulses. A second transistor is turned on with the second drive pulses. A current flows in response to an on-time state of the first transistor overlapping with an on-time state of the second transistor. A delay of the second drive pulses is decreased based on a time of the current flow overlapping with one of the first initial pulses; and the delay of the second drive pulses is increased based on the time of the current flow overlapping with one of the second initial pulses.

Detecting voltage-based attacks on an integrated circuit (IC) is difficult in the presence of clock jitter. Propagating signals can exhibit a total delay that is due to a delay component resulting from a voltage-based attack and a delay characteristic resulting from clock fluctuation. Voltage-variation detection circuitry includes first and second voltage-dependent circuits and a voltage analysis circuit. The voltage-dependent circuits produce first and second signals that are indicative of a voltage level responsive to a clock signal and based on different first and second voltage sensitivities. The voltage analysis circuit generates a voltage alert signal based on the first and second signals. A combined signal neutralizes the delay characteristic in the first and second signals, but the delay component due to the voltage variation can be at least partially maintained. Thus, a voltage-based attack is detectable in the presence of clock fluctuation by using two voltage-dependent circuits.

A detection circuit configured to detect whether timing violations occur in a target circuit. The target circuit is operated according a clock signal. The detection circuit includes a signal generation circuit, a first delay adjustable circuit, a second delay adjustable circuit, and a signal detector. The signal generation circuit is configured to generate a test signal. The first and second delay adjustable circuit are respectively configured to delay the test signal and clock signal to generate a first delay signal and a second delay signal according to the operating speed of the target circuit. The signal detector is configured to generate an indicating signal according to the first delay signal, the second delay signal, the test signal, and the clock signal. The indicating signal is configured to indicate whether an operating voltage of the target circuit causes a hold time violation of timing violations to occur in the target circuit.

According to an embodiment, a storage device includes a plurality of storage elements, a plurality of readout circuits, and a delay circuit. The readout circuits include a first readout circuit and a second readout circuit different from the first readout circuit. The readout circuits each determines data stored in a corresponding one of the storage elements and outputs a result of the determination, in response to receipt of an activation signal. The delay circuit is connected at a first end to the first readout circuit and connected at a second end to the second readout circuit. The delay circuit supplies the activation signal to the second readout circuit with a time interval after supplying the activation signal to the first readout circuit.