Embodiments include apparatuses, methods, and systems for jitter equalization and phase error detection. In embodiments, a communication circuit may include a data path to pass a data signal and a clock path to pass a clock signal. A jitter equalizer may be coupled with the data path and/or clock path to provide a programmable delay to the data signal and/or clock signal, respectively. The delay may be determined by a training process in which a supply voltage may be modulated by a modulation frequency. The delay may be dependent on a value of the supply voltage, such as a voltage level and/or jitter frequency component of the supply voltage. A phase error detector is also described that may be used with the communication circuit and/or other embodiments.

Disclosed is a device for detecting the margin of a circuit operating at an operating speed. The device includes: a signal generating circuit generating an input signal including predetermined data; a first adjustable delay circuit delaying the input signal by a first delay amount and thereby generating a delayed input signal; a circuit under test performing a predetermined operation based on a predetermined operation timing and thereby generating a to-be-tested signal according to the delayed input signal; a second adjustable delay circuit delaying the to-be-tested signal by a second delay amount and thereby generating a delayed to-be-tested signal; a comparison circuit comparing the data included in the delayed to-be-tested signal with the predetermined data based on the predetermined operation timing and thereby generating a comparison result; and a calibration circuit determining whether the circuit under test passes a speed test according to the comparison result.

The data serialization circuit includes a delay circuit, a data serializer, a first data sampler and a second data sampler. The delay circuit receives an input clock signal and generates a plurality of delayed clock signals. The delayed clock signals includes a first delayed clock signal generated by a first delay stage and a second delayed clock signal generated by a second delay stage. The data serializer receives parallel data and a final stage delayed clock signal of the delayed clock signals, and converts the parallel data into serial data according to the final stage delayed clock signal. Wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal to generate a second output serial data.

An integrated circuit may be provided. The integrated circuit may include a transmitter and a receiver. The transmitter outputs first transmission data to a first channel and outputs second transmission data to a second channel. The phase of the first transmission data transmitted through the first channel is different from a phase of the second transmission data transmitted through the second channel.

There are provided a signal width repair circuit and method, and an electronic device. The signal width repair circuit includes: a delay circuit, configured to receive an input signal, and delay the input signal for a preset duration to obtain a delayed signal, the input signal being a high-level signal; a signal reconstruction circuit, configured to receive the input signal and the delayed signal, and repair the input signal and the delayed signal to obtain a repaired signal; and a signal selection circuit, configured to receive the input signal and the repaired signal and select one of the input signal and the repaired signal for output, to obtain a target signal that has a width satisfying a preset width, the preset duration being equal to or greater than a duration with the preset width.

Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example apparatus includes a shift register that includes a plurality of registers coupled in series to one another. The plurality of registers are grouped into a first group of registers and a second group of registers. The first group of registers includes first and second registers. The second group of registers includes a third register. The first and second registers of the first group of registers are configured to receive in common an output of the third register of the second group of registers so that both the first and second registers store the output of the third register responsive to a shift clock.

Aspects of the disclosure are directed to adaptively delaying an input signal. In accordance with one aspect, an apparatus includes a plurality of delay units, wherein each of the plurality of delay units includes a substantially similar output load characteristic; a plurality of buffer units, wherein each of the plurality of buffer units is coupled to one of the plurality of delay units; wherein a quantity of the plurality of delay units equals a quantity of the plurality of buffer units; an additional delay unit coupled to a delay unit output of one of the plurality of delay units; and a one-hot decoder coupled to each of the plurality of buffer units, the one-hot decoder configured to enable one and only one of the plurality of buffer units.

Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.

In described examples, an electronic circuit for determining a phase difference between a first clock signal and a second clock signal includes a timer circuit, circuitry for generating a selectively delayed transition of the second clock signal, and phase determination circuitry. The timer circuit produces an elapsed time between a transition of the first clock signal and the selectively delayed transition of the second clock signal. The circuitry for generating the selectively delayed transition of the second clock signal generates the selectively delayed transition in response to a random selection of a respective output from a plurality of second clock signal delay stages. The phase determination circuitry provides the phase difference in response to the elapsed time and the random selection of a respective output from a plurality of second clock signal delay stages.

A clock compensation circuit includes a delay circuit configured to generate a plurality of second clock signals by delaying a plurality of first clock signals, a voltage conversion circuit configured to convert phase differences between the plurality of second clock signals into voltages and output converted voltages as a plurality of phase difference voltages, and a comparison circuit configured to generate a plurality of phase difference detection signals by comparing the plurality of phase difference voltages with a reference voltage. The clock compensation circuit also includes a phase error control circuit configured to generate a plurality of control signals for controlling the delay circuit, the voltage conversion circuit, and the comparison circuit according to any of the plurality of second clock signals and the plurality of phase difference detection signals.