Example implementations described herein are directed to reducing far end cross talk (FEXT), including differential-to-differential far end crosstalk (DDFEXT) or single ended FEXT through generating and applying a delay shifter/inverter that is cascaded onto a target electrical system and shifts the even-mode and odd-mode propagation delay of a target electrical system to be substantially equal, which in turn reduces FEXT in the overall system.

A low-power synchronizer circuit, a data processing circuit that incorporates the synchronizer circuit, and a synchronization method are provided. The synchronizer circuit includes a delay circuit for receiving and delaying an asynchronous input signal, a first flip-flop having an input terminal connected to an output terminal of the delay circuit, a clock terminal for receiving the asynchronous input signal, and a reset terminal for receiving the asynchronous input signal, a synchronizer connected to an output terminal of the first flip-flop, and a clock-gating circuit for receiving a clock signal and determining whether to supply the clock signal to the synchronizer in response to one of a first output value of the delay circuit and a second output value of the first flip-flop and a third output value of the synchronizer.

A signal generation device outputs a signal based on a predetermined pattern with a logic transition to a predetermined external device. The signal generation device comprises an output driver which outputs respective signals based on at least two test patterns different in the frequency of the logic transition respectively to the predetermined external device, a regulator which supplies power to the output driver, a current compensation circuit which generates a compensation current, and a control circuit which adjusts a value of the compensation current. The control circuit adjusts, for each test pattern, the value of the compensation current such that a difference value calculated based on output voltages of the regulator becomes a determination criteria value or less.

An object of the present invention is to reduce burden on a program for changing an operation mode of an internal circuit in accordance with an internal clock frequency without mounting a large-scale circuit in an LSI in which setting of the frequency of an internal clock can be dynamically changed. In an LSI including an internal clock generation circuit generating an internal clock from a clock source in accordance with a parameter supplied, a register storing frequency information of the clock source, a register storing the parameter, and an internal circuit having a plurality of operation modes, a table circuit controlling the operation mode of the internal circuit in association with the frequency information and the parameter supplied from the registers is provided.

A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

A device includes a clock delay circuit configured to receive a reference clock signal and generate N delay clock signals, where N is a natural number greater than or equal to 2, by using the reference clock signal, and an output circuit configured to receive the N delay clock signals and output at least a portion of the delay clock signals from among the N delay clock signals as an output signal, wherein a phase delay of a delay clock signal that is output later in time from among the at least the portion of the delay clock signals is greater than or equal to a phase delay of a delay clock signal that is output earlier in time, and wherein a cycle of the output clock signal is longer than or equal to a cycle of the reference clock signal.

A pure digital ring oscillator with constant power consumption as oscillation frequency is adjusted. Circuit topology includes a multiplexer implemented in NAND gates and a delay element positioned after a path selection NAND gate of that multiplexer such that delay element transistors may not toggle if the non-delaying signal path is selected. Assuming a delay element oscillation frequency f and a total capacitance C, and also assuming a plurality N of delay gates each characterized by a propagation delay t1 and a capacitance C1 such that C=C1*N, the ring oscillator of the present invention is characterized by a C value that is proportional to N and an f value that is inversely proportional to N. Furthermore, each of the N delay gates as well as the input and output gates of the multiplexer are characterized by a common capacitance-to-propagation delay ratio=C1/t1.

A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

Provided is a selectable delay buffer for tuning a delay path in a circuit. The selectable delay buffer comprises a first delay segment configured to pass an input signal to an output terminal within a first range of time delays, a second delay segment configured to pass the input signal to the output terminal within a second range of time delays that is different from the first range, and a segment selection switch configured to selectively couple the delay segments to the output terminal based on received selection information that indicates which delay segment to couple to the output terminal.

With respect to a phase locked loop (PLL) circuit that receives a first reference clock and generates an output clock, the PLL circuit includes a delay circuit that delays the first reference clock to generate a second reference clock, a feedback circuit that generates a control signal based on a phase difference between the second reference clock and a feedback clock, an oscillator that oscillates at a frequency determined based on the control signal to generate the output clock, and a divider that divides the output clock in the on state. The PLL circuit switches between a first mode and a second mode, the feedback clock in the first mode is a signal obtained by retiming an output of the divider with the output clock, and the feedback clock in the second mode is a signal obtained by retiming the first reference clock with the output clock.