A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

A programmable delay line includes a pulse generator configured to generate a pulse in response to a transition of an input signal; an oscillator configured to generate a clock in response to the pulse; a counter configured to change a current count from a first value towards a second value in response to periods of the clock; and a gating device configured to output the transition of the input signal to generate an output signal in response to the current count reaching the second value. The delay of the input signal is a function of the difference between the first value and the second value. The delay line may be used in different applications, such as a dynamic variation monitor (DVM) configured to detect supply voltage droop. The DVM may be in an adaptive clock distribution (ACD) to reduce the clock frequency for a datapath in response to a droop.

A circuit and corresponding method enable glitch-free frequency. The circuit comprises a first delay circuit and a second delay circuit, configured to produce first and second propagated enables, respectively, from first and second input enables, respectively; and an output clock circuit. The output clock circuit is configured to produce an output clock that switches, glitch-free, between a first phase-locked clock and a second phase-locked. The first and second delay circuits are further configured to enable the output clock to be switched, glitch-free, by employing the second propagated enable to gate propagation of the first input enable and the first propagated enable to gate propagation of the second input enable, respectively. The first and second input enables are configured to be enabled, alternately, causing the output clock to switch between the first and second phase-locked clocks.

A burn-in resilient integrated circuit is provided. The burn-in resilient integrated circuit includes an inverter chain and a plurality of inverter circuits on the inverter chain. The burn-in resilient integrated circuit also includes a loop providing an electrical connection from an output of the inverter chain to an input of the inverter chain. The loop is selectable in accordance with a burn-in operation.

The present disclosure provides a device for signal delay. The device comprises: a frame of insulation material; multiple signal electrodes provided in the frame and electrically connected to each other in series; an input terminal electrically connected to a first of the multiple signal electrodes and configured to receive an input signal; and an output terminal electrically connected to a second of the multiple signal electrodes and configured to output an output signal that is delayed by the multiple signal electrodes with respect to the input signal, wherein at least one of the multiple signal electrodes is located at a different height than those of other signal electrodes with respect to a surface on which the device is to be mounted.

According to one embodiment, an information processing device, includes: a digital-to-pulse converter configured to output a pulse signal including a pulse with a pulse length corresponding to a digital input signal; and a bidirectional selective oscillator including a first ring oscillator and a second ring oscillator, the first ring oscillator including a plurality of delay elements connected in a ring shape in a first direction, the second ring oscillator including a plurality of delay elements connected in a ring shape in a second direction reverse to the first direction. The bidirectional selective oscillator is configured to select one of the first ring oscillator and the second ring oscillator depending on a sign of the digital input signal, oscillate the selected ring oscillator during a period when the pulse is outputted, and keep a state of oscillation operation when the pulse stops being outputted.

A clock generation circuit includes: a frequency detector suitable for generating an internal clock, and generating a counting signal indicating a toggling number of the internal clock during an activation period of an input clock; a control signal generator suitable for generating a plurality of period control signals based on a target signal and the counting signal, the target signal indicating a target frequency of an output clock; and a period controller suitable for generating the output clock based on the period control signals.

A power-up initialization circuit includes a delay chain circuit and a signal generator circuit. The delay chain circuit receives a power supply voltage, and applies a predetermined delay amount to the power supply voltage for generating a delayed output voltage. The signal generator circuit receives the delayed output voltage from the delay chain circuit, and generates and outputs at least one power-up initialization signal in response to the delayed output voltage.

Devices and methods are provided for monitoring a transient time in a device under test. A circuit includes a transient edge clipper circuit electrically coupled to the device under test. The transient edge clipper circuit is configured to remove voltage levels of a voltage waveform of the device under test which exceed a threshold range to generate a clipped voltage waveform. The circuit also includes logic circuitry electrically coupled to the transient edge clipper circuit. The logic circuitry is configured to generate a time delayed pulse signal representation of the clipped voltage waveform by injecting a predetermined time delay. The circuit also includes a converter circuit electrically coupled to the logic circuitry. The converter circuit is configured to generate a current signal based on the pulse signal representations.

Devices and methods are provided for monitoring a transient time in a device under test. A circuit includes a transient edge clipper circuit electrically coupled to the device under test. The transient edge clipper circuit is configured to remove voltage levels of a voltage waveform of the device under test which exceed a threshold range to generate a clipped voltage waveform. The circuit also includes logic circuitry electrically coupled to the transient edge clipper circuit. The logic circuitry is configured to generate a time delayed pulse signal representation of the clipped voltage waveform by injecting a predetermined time delay. The circuit also includes a converter circuit electrically coupled to the logic circuitry. The converter circuit is configured to generate a current signal based on the pulse signal representations.