An object of the disclosure is to provide a slope enhancement circuit, comprising an amplifier and a specific arrangement of capacitors and switches, further comprising a current digital to analog converter (IDAC), in a switched regulated current mirror. A method of sample and hold exploits the transient dynamics of the switched current mirror, to enhance the output current slope during PWM operation. A further object of the disclosure is to provide a low power, high speed switching type of regulated current mirror architecture. Still further, another object of the disclosure is to provide quick response to a sudden demand in current with a high degree of accuracy. Still further, another object of the disclosure is to provide a significant savings in circuit area.

An integrated circuit (IC) device includes a first input/output (I/O) buffer circuit. The first input/output buffer circuit includes first and second groups of stacked transistors. The first group of stacked transistors transfer signals formatted in accordance with only one signal protocol from the group of signal protocols. The second group of stacked transistors transfers the signals formatted in accordance with more than one signal protocols. In addition, integrated circuit device also includes a second input/output buffer circuit. The second input/output buffer circuit includes third and fourth groups of stacked transistors. The third group of stacked transistors transfers the signals formatted in accordance to the first signal transmission protocol from the group of signal transmission protocols. The fourth group of stacked transistors transfers the signals formatted in accordance to the plurality of signal transmission protocols from the group of signal transmission protocols.

An integrated circuit (IC) device includes a first input/output (I/O) buffer circuit. The first input/output buffer circuit includes first and second groups of stacked transistors. The first group of stacked transistors transfer signals formatted in accordance with only one signal protocol from the group of signal protocols. The second group of stacked transistors transfers the signals formatted in accordance with more than one signal protocols. In addition, integrated circuit device also includes a second input/output buffer circuit. The second input/output buffer circuit includes third and fourth groups of stacked transistors. The third group of stacked transistors transfers the signals formatted in accordance to the first signal transmission protocol from the group of signal transmission protocols. The fourth group of stacked transistors transfers the signals formatted in accordance to the plurality of signal transmission protocols from the group of signal transmission protocols.

An integrated circuit device includes a substrate, a voltage monitor circuit formed on the substrate, and a trimming circuit formed on the substrate that includes a successive approximation register circuit having an input coupled to an output of the voltage monitor circuit; a beta multiplier circuit having an input coupled to an output of the successive approximation register circuit, an output coupled to a first input of the voltage monitor circuit, and a variable resistance circuit. A resistance value of the variable resistance circuit is controlled by the output of the successive approximation register.

An integrated circuit device includes a substrate, a voltage monitor circuit formed on the substrate, and a trimming circuit formed on the substrate that includes a successive approximation register circuit having an input coupled to an output of the voltage monitor circuit; a beta multiplier circuit having an input coupled to an output of the successive approximation register circuit, an output coupled to a first input of the voltage monitor circuit, and a variable resistance circuit. A resistance value of the variable resistance circuit is controlled by the output of the successive approximation register.

An integrated circuit device includes a substrate, a voltage monitor circuit formed on the substrate, and a trimming circuit formed on the substrate that includes a successive approximation register circuit having an input coupled to an output of the voltage monitor circuit; a beta multiplier circuit having an input coupled to an output of the successive approximation register circuit, an output coupled to a first input of the voltage monitor circuit, and a variable resistance circuit. A resistance value of the variable resistance circuit is controlled by the output of the successive approximation register.

An integrated circuit device includes a substrate, a voltage monitor circuit formed on the substrate, and a trimming circuit formed on the substrate that includes a successive approximation register circuit having an input coupled to an output of the voltage monitor circuit; a beta multiplier circuit having an input coupled to an output of the successive approximation register circuit, an output coupled to a first input of the voltage monitor circuit, and a variable resistance circuit. A resistance value of the variable resistance circuit is controlled by the output of the successive approximation register.

An object of the disclosure is to provide a slope enhancement circuit, comprising an amplifier and a specific arrangement of capacitors and switches, further comprising a current digital to analog converter (IDAC), in a switched regulated current mirror. A method of sample and hold exploits the transient dynamics of the switched current mirror, to enhance the output current slope during PWM operation. A further object of the disclosure is to provide a low power, high speed switching type of regulated current mirror architecture. Still further, another object of the disclosure is to provide quick response to a sudden demand in current with a high degree of accuracy. Still further, another object of the disclosure is to provide a significant savings in circuit area.

An object of the disclosure is to provide a slope enhancement circuit, comprising an amplifier and a specific arrangement of capacitors and switches, further comprising a current digital to analog converter (IDAC), in a switched regulated current mirror. A method of sample and hold exploits the transient dynamics of the switched current mirror, to enhance the output current slope during PWM operation. A further object of the disclosure is to provide a low power, high speed switching type of regulated current mirror architecture. Still further, another object of the disclosure is to provide quick response to a sudden demand in current with a high degree of accuracy. Still further, another object of the disclosure is to provide a significant savings in circuit area.

An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.