An integrated circuit (IC) includes an input/output (I/O) circuitry with a first circuitry section including I/O pins and a second circuitry section including I/O pins. The first and second circuitry sections are mutually exclusive sections of the I/O ring. The first circuitry section includes a first I/O pin configured to receive an input voltage from a first energy source and a second I/O pin connectable to an external startup capacitor. A startup circuit is coupled to the first I/O pin and the second I/O pin. Upon receiving the input voltage from the first energy source, the startup circuit enters a during the startup phase and isolates the first circuitry section from the second circuitry section, and provides charge to the external startup capacitor. In response to achieving a predetermined minimum charge on the external startup capacitor, the first circuitry section is connected to the second circuitry section, and the startup phase ends and the IC transitions to a functional mode of operation.

An integrated circuit (IC) includes an input/output (I/O) circuitry with a first circuitry section including I/O pins and a second circuitry section including I/O pins. The first and second circuitry sections are mutually exclusive sections of the I/O ring. The first circuitry section includes a first I/O pin configured to receive an input voltage from a first energy source and a second I/O pin connectable to an external startup capacitor. A startup circuit is coupled to the first I/O pin and the second I/O pin. Upon receiving the input voltage from the first energy source, the startup circuit enters a during the startup phase and isolates the first circuitry section from the second circuitry section, and provides charge to the external startup capacitor. In response to achieving a predetermined minimum charge on the external startup capacitor, the first circuitry section is connected to the second circuitry section, and the startup phase ends and the IC transitions to a functional mode of operation.

A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.

A digital clock multiplier (DCM) circuit including: a plurality of power amplifier (PA) rows, wherein each PA row comprises a plurality of cascade switched capacitor power amplifiers (SCPA) unit cells configured to: receive a phase shift of a driving clock phase; and one or more processors configured to: disable of one or more of the plurality of cascade SCPA unit cells based on a frequency of the phase shift; generate an output signal for each of the cascade SCPA unit cells; and combine the output signal for each of the cascade SCPA unit cells to generate an PA row output signal.

The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

An electronic device has an amplifier having an amplifier input terminal and an amplifier output terminal, the amplifier output terminal being connected to the device output terminal. An input capacitor is connected between the device input terminal and the amplifier input terminal. A feedback capacitor is connected between the amplifier output terminal and the amplifier input terminal. A switchable capacitor has a first terminal connected to the amplifier input terminal and a second terminal connected to a respective first terminal of each of a first switch and a second switch. The first switch has its second terminal connected to the device input terminal. The second switch has its second terminal connected to the amplifier output terminal. In this arrangement, the switchable capacitor can be switched between forming part of the input path of the amplifier or the feedback path of the amplifier.

An electronic device has an amplifier having an amplifier input terminal and an amplifier output terminal, the amplifier output terminal being connected to the device output terminal. An input capacitor is connected between the device input terminal and the amplifier input terminal. A feedback capacitor is connected between the amplifier output terminal and the amplifier input terminal. A switchable capacitor has a first terminal connected to the amplifier input terminal and a second terminal connected to a respective first terminal of each of a first switch and a second switch. The first switch has its second terminal connected to the device input terminal. The second switch has its second terminal connected to the amplifier output terminal. In this arrangement, the switchable capacitor can be switched between forming part of the input path of the amplifier or the feedback path of the amplifier.

An amplitude modulation circuit includes: first, second, and third input terminals; first and second output terminals; a current source; first and second transistors including a base electrically connected to the first and second input terminals, a collector electrically connected to the first and second output terminals, and an emitter electrically connected to a grounding terminal via the current source; first and second resistive elements electrically connected between the first and second output terminals and a power line; and a first MOS transistor including a drain connected to the first output terminal, a source connected to the second output terminal, and a gate connected to the third input terminal. The MOS transistor is configured to operate in a non-saturated region, and a resistance between the source and the drain of the MOS transistor is larger than resistances of the first and second resistive elements.

An amplitude modulation circuit includes: first, second, and third input terminals; first and second output terminals; a current source; first and second transistors including a base electrically connected to the first and second input terminals, a collector electrically connected to the first and second output terminals, and an emitter electrically connected to a grounding terminal via the current source; first and second resistive elements electrically connected between the first and second output terminals and a power line; and a first MOS transistor including a drain connected to the first output terminal, a source connected to the second output terminal, and a gate connected to the third input terminal. The MOS transistor is configured to operate in a non-saturated region, and a resistance between the source and the drain of the MOS transistor is larger than resistances of the first and second resistive elements.