A device includes a combining circuitry that receives an incoming signal, and one or more delayed signals from a delay circuitry. The combining circuitry combines the incoming signal and the one or more delayed signals to generate a combined signal. The device includes a comparing circuitry that receives the combined signal from the combining circuitry, and compares a pulse width of the combined signal to a threshold pulse width. When the pulse width of the combined signal is greater than or equal to the threshold pulse width, the comparing circuitry provides the combined signal to an amplifier circuit and provides a null signal to the delay circuitry. The amplifier circuit generates a pulse width modulated (PWM) signal based on the combined signal.

An example a phase-locked loop (PLL) circuit includes a sampling phase detector configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider configured to generate the reference clock from the output clock.

An example a phase-locked loop (PLL) circuit includes a sampling phase detector configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider configured to generate the reference clock from the output clock.

The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

A semiconductor device includes an amplifier, a slew rate regulating circuit, a detection circuit, and a control circuit. The amplifier is configured to amplify an input signal. The slew rate regulating circuit is configured to regulate the slew rate of the input signal. The detection circuit is configured to detect the slew rate of the input signal along a signal path of the input signal between the slew rate regulating circuit and the amplifier. The control circuit is configured to control the slew rate regulating circuit based on a detection result of the detection circuit.

A semiconductor device includes an amplifier, a slew rate regulating circuit, a detection circuit, and a control circuit. The amplifier is configured to amplify an input signal. The slew rate regulating circuit is configured to regulate the slew rate of the input signal. The detection circuit is configured to detect the slew rate of the input signal along a signal path of the input signal between the slew rate regulating circuit and the amplifier. The control circuit is configured to control the slew rate regulating circuit based on a detection result of the detection circuit.

In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.

A switched driver for a power supply includes a high-side switch and a low-side switch coupled to the high-side switch. An output is coupled between the high-side switch and the low-side switch. A switch controller is coupled to either the high-side switch or the low-side switch and has a switch controller input for receiving a switch control signal and an output for controlling a switch. The switch controller initially reduces the resistance of the switch, increases the resistance of the switch, and then reduces the resistance of the switch in response to a signal received at the input.

A switched driver for a power supply includes a high-side switch and a low-side switch coupled to the high-side switch. An output is coupled between the high-side switch and the low-side switch. A switch controller is coupled to either the high-side switch or the low-side switch and has a switch controller input for receiving a switch control signal and an output for controlling a switch. The switch controller initially reduces the resistance of the switch, increases the resistance of the switch, and then reduces the resistance of the switch in response to a signal received at the input.

There are provided a signal width repair circuit and method, and an electronic device. The signal width repair circuit includes: a delay circuit, configured to receive an input signal, and delay the input signal for a preset duration to obtain a delayed signal, the input signal being a high-level signal; a signal reconstruction circuit, configured to receive the input signal and the delayed signal, and repair the input signal and the delayed signal to obtain a repaired signal; and a signal selection circuit, configured to receive the input signal and the repaired signal and select one of the input signal and the repaired signal for output, to obtain a target signal that has a width satisfying a preset width, the preset duration being equal to or greater than a duration with the preset width.