In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells have a high input threshold approximately equal to Vdd and a low input threshold approximately equal to Vss to increase delay through each cell. An output buffer receives a phase signal from an output terminal of one of the Schmitt trigger delay cells and converts a transition phase signal to a faster transition clock signal. The output buffer has control circuitry that generates non-overlapping control signals in response to the phase signal, to control an output stage to generate the fast transition clock signal while preventing short circuit current in the output stage.

In described examples of an integrated circuit (IC), an oscillator includes Schmitt trigger delay cells connected in a ring topology. The Schmitt trigger delay cells have a high input threshold approximately equal to Vdd and a low input threshold approximately equal to Vss to increase delay through each cell. An output buffer receives a phase signal from an output terminal of one of the Schmitt trigger delay cells and converts a transition phase signal to a faster transition clock signal. The output buffer has control circuitry that generates non-overlapping control signals in response to the phase signal, to control an output stage to generate the fast transition clock signal while preventing short circuit current in the output stage.

An embodiment in accordance with the present invention provides a system and method of physically modulating a digital signal across a medium. A signal is sent one bit at a time (serially) as a period of high voltage followed by a period of low voltage. The present invention includes several major advantages. One advantage is that the code to execute the method is very lightweight. Another advantage is that the signals require no synchronization source. The signals of the present invention function as their own synchronization.

An embodiment in accordance with the present invention provides a system and method of physically modulating a digital signal across a medium. A signal is sent one bit at a time (serially) as a period of high voltage followed by a period of low voltage. The present invention includes several major advantages. One advantage is that the code to execute the method is very lightweight. Another advantage is that the signals require no synchronization source. The signals of the present invention function as their own synchronization.

Many embodiments provide a frequency comb receiver that includes a PIN diode, a THz pulse generator block that generates THz tones (LO) for coherent frequency comb detection, an on-chip antenna for broadband detection and a driver stage switched by a series of buffers, where a repetition rate of the LO tones are tunable over a range and determines a spacing between two adjacent tones in the corresponding frequency comb.

A pulse signal sending circuit that outputs pulse signals from an output terminal includes: an output transistor; an inverter circuit; and a delay circuit. The output transistor includes a drain terminal connected to the output terminal. The inverter circuit is connected to a gate terminal of the output transistor and outputs a signal to be input to the gate terminal of the output transistor. The delay circuit receives a pulse signal as an input and delays rising or falling of the input pulse signal. The pulse signal delayed by the delay circuit is input to the inverter circuit.

An apparatus comprises a plurality of power sources, one or more processors embedded with the plurality of power sources, and memory storing processor executable instructions that, when executed by the one or more processors, cause the apparatus to modify duty cycles of the power sources, and to modify timing for each phase of a multiphase cycle. In some cases, the apparatus: transfers, for each phase of the multiphase cycle, power from a different power source of a plurality of power sources to a load; determines, for each phase of the multiphase cycle, an input voltage associated with the transferred power, an output voltage associated with the transferred power, and current from the power source associated with the transferred power; determines a duty cycle associated with the power source; modifies duty cycles of the power sources; and modifies timing for each phase of the multiphase cycle.

An apparatus comprises a plurality of power sources, one or more processors embedded with the plurality of power sources, and memory storing processor executable instructions that, when executed by the one or more processors, cause the apparatus to modify duty cycles of the power sources, and to modify timing for each phase of a multiphase cycle. In some cases, the apparatus: transfers, for each phase of the multiphase cycle, power from a different power source of a plurality of power sources to a load; determines, for each phase of the multiphase cycle, an input voltage associated with the transferred power, an output voltage associated with the transferred power, and current from the power source associated with the transferred power; determines a duty cycle associated with the power source; modifies duty cycles of the power sources; and modifies timing for each phase of the multiphase cycle.

There are provided a signal width repair circuit and method, and an electronic device. The signal width repair circuit includes: a delay circuit, configured to receive an input signal, and delay the input signal for a preset duration to obtain a delayed signal, the input signal being a high-level signal; a signal reconstruction circuit, configured to receive the input signal and the delayed signal, and repair the input signal and the delayed signal to obtain a repaired signal; and a signal selection circuit, configured to receive the input signal and the repaired signal and select one of the input signal and the repaired signal for output, to obtain a target signal that has a width satisfying a preset width, the preset duration being equal to or greater than a duration with the preset width.

A driving circuit (10) to generate a signal pulse for operating a light-emitting diode (20) comprises an external terminal (LEDK, LEDA) to connect the light-emitting diode (20) to the driving circuit (10). In a first operating state/pre-charge state of the driving circuit (10), a first controllable switching circuit (100) connects a first side (301) of a capacitor (300) to a reference potential (Vref) and a second controllable switch (200) connects a second side (302) of the capacitor (300) to one of a supply and ground potential (VDD, VSS). In a second operating state of the driving circuit (10), the first controllable switching circuit (100) connects the first side (301) of the capacitor (300) to said one of the supply and ground potential (VDD, VSS) and the second controllable switch (200) connects the second side (302) of the capacitor (300) to the external terminal (LEDK, LEDA) to provide a signal pulse for operating the light emitting diode.