The disclosure is directed to a power module apparatus that includes a base plate, a power substrate positioned relative to the base plate, at least two power contacts, a gate-source board mounted relative to the power substrate, gate drive connectors electrically connected to the gate-source board, a housing secured to the power substrate, and a clamping circuit electrically connected to the at least one power device. The clamping circuit being configured to clamp an input to a gate of the at least one power device. The clamping circuit being arranged with at least one of the following: the base plate, the power substrate, one of the at least two power contacts, the at least one power device, the gate-source board, the gate drive connectors, and the housing. The disclosure is further directed to a process of configuring a power module apparatus.

The disclosure is directed to a power module apparatus that includes a base plate, a power substrate positioned relative to the base plate, at least two power contacts, a gate-source board mounted relative to the power substrate, gate drive connectors electrically connected to the gate-source board, a housing secured to the power substrate, and a clamping circuit electrically connected to the at least one power device. The clamping circuit being configured to clamp an input to a gate of the at least one power device. The clamping circuit being arranged with at least one of the following: the base plate, the power substrate, one of the at least two power contacts, the at least one power device, the gate-source board, the gate drive connectors, and the housing. The disclosure is further directed to a process of configuring a power module apparatus.

In a solid-state image sensor provided with a comparator that compares a reference signal and a pixel signal, the image quality of image data is improved. A voltage divider circuit supplies a divided voltage of an input voltage and a predetermined reference voltage that are input. An input-side differential transistor outputs a drain current corresponding to the gate-source voltage between the divided voltage input to the gate and a predetermined source voltage. An output-side differential transistor outputs a voltage corresponding to the drain current as a result of comparison between the input voltage and the reference voltage. A control transistor reduces the gate-source voltage in a case where the input voltage is out of a predetermined range.

A comparator circuit includes a first comparator configured to receive input of an input signal and a comparison target signal to be compared with the input signal, a first output stage including an N-channel transistor having a control terminal to which a first control terminal voltage output from the first comparator is applied, and a first clamp unit configured to limit the first control terminal voltage to be not higher than a first predetermined voltage that is higher than a first threshold voltage of the N-channel transistor but is lower than a first high side voltage output as high level from the first comparator when the first control terminal voltage is not limited.

A comparator circuit includes a first comparator configured to receive input of an input signal and a comparison target signal to be compared with the input signal, a first output stage including an N-channel transistor having a control terminal to which a first control terminal voltage output from the first comparator is applied, and a first clamp unit configured to limit the first control terminal voltage to be not higher than a first predetermined voltage that is higher than a first threshold voltage of the N-channel transistor but is lower than a first high side voltage output as high level from the first comparator when the first control terminal voltage is not limited.

Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

Various embodiments of the present technology may provide methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may provide an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

An illustrative receiver includes: a decision element that derives symbol decisions from a slicer input signal; an equalizer that converts a receive signal into the slicer input signal; a summer that combines the symbol decisions with the slicer input signal to produce an error signal; and a level finder that operates on said signals to determine thresholds at which each signal has a given probability of exceeding the threshold. One illustrative level finder circuit includes: a gated comparator and an asymmetric accumulator. The gated comparator asserts a first or a second gated output signal to indicate when an input signal exceeds or falls below a threshold with a programmable condition being met. The asymmetric accumulator adapts the threshold using up steps for assertions of the first gated output signal and down steps for assertions of the second gated output signal, with the up-step size being different than the down-step size.

A gate driver circuit includes first through third transistors, a first voltage clamp, and control logic. The first transistor has a first control input and first and second current terminals. The first current terminal couples to a first voltage terminal. The first voltage clamp couples between the first voltage terminal and the first control input. The second transistor couples between the first control input and the second voltage terminal. The third transistor couples between the first control input and the second voltage terminal. The third transistor is smaller than the second transistor. The control logic is configured to turn on both the second and third transistors to thereby turn on the first transistor, and the first control logic configured to turn off the second transistor after the first transistor turns on while maintaining in an on-state the third transistor to maintain the first transistor in the on-state.

Circuits and methods for generating a bypass pulse to an RF circuit that increases the response time of the circuit to mode changes. Embodiments include a pulse generation circuit that it is self-initiated and self-terminated, generating a bypass pulse as a function of voltages V1 and V2 along a signal path. Voltage V3, a scaled version of V1, is compared to a voltage V4 derived from V2 and a pulse is output while V3>V4. The pulse temporarily lowers the signal path impedance, reducing the RC time constant of the signal path and allowing fast charging of components coupled to the signal path. The pulse may be used with any other circuit that needs a faster settling time after a mode change but is slowed down by an RC time constant. Usage also extends to providing for rapid discharge of the signal path by adding additional logic components.