An intrusion detection apparatus and method thereof are provided. The intrusion detection apparatus includes a status detection device, a front-end signal processor, a delay device, and a signal sampler. The status detection device is configured to generate an indicating signal according to an opened status of the case. The front-end signal processor receives the indicating signal and performs a noise filtering function on the indicating signal so as to generate a processed indicating signal. The delay device delays the processed indicating signal to generate a delayed indicating signal. The signal sampler samples the processed indicating signal to generate a detection result according to the delayed indicating signal.

Identifying frequencies to be protected at a victim integrated circuit (IC) and sending protection information including the identified frequencies to an aggressor IC. The aggressor IC configures its subsystems or circuits to operate using operating frequencies that prevents spurs that may interfere with the frequencies identified in the protection information. If not all of the frequencies in the protection information can be protected, the aggressor IC selects a subset of the frequencies to be protected. Then, the aggressor IC configures the operating frequencies of its subsystems or circuits so that spurs that they generate do not interfere with the selected frequencies.

Identifying frequencies to be protected at a victim integrated circuit (IC) and sending protection information including the identified frequencies to an aggressor IC. The aggressor IC configures its subsystems or circuits to operate using operating frequencies that prevents spurs that may interfere with the frequencies identified in the protection information. If not all of the frequencies in the protection information can be protected, the aggressor IC selects a subset of the frequencies to be protected. Then, the aggressor IC configures the operating frequencies of its subsystems or circuits so that spurs that they generate do not interfere with the selected frequencies.

A compensation signal generator generates a compensation signal for canceling an electromagnetic noise on a connection line on the basis of a detection signal of a noise detector. A compensation signal injector injects the compensation signal into the connection line. A compensation signal detector outputs a detection signal of the compensation signal. A low-frequency component subtraction unit amplifies a component in a predetermined first frequency region of the detection signal and negatively feeds back the amplified component to the compensation signal generator. An intermediate frequency component addition unit positively feeds back a component of a predetermined second frequency that is higher than the first frequency region in the detection signal to the compensation signal generator.

A compensation signal generator generates a compensation signal for canceling an electromagnetic noise on a connection line on the basis of a detection signal of a noise detector. A compensation signal injector injects the compensation signal into the connection line. A compensation signal detector outputs a detection signal of the compensation signal. A low-frequency component subtraction unit amplifies a component in a predetermined first frequency region of the detection signal and negatively feeds back the amplified component to the compensation signal generator. An intermediate frequency component addition unit positively feeds back a component of a predetermined second frequency that is higher than the first frequency region in the detection signal to the compensation signal generator.

A motor control system includes a DC motor and a ripple count circuit. The DC motor includes a rotor that rotates in response to a drive current. The rotation of the rotor generates a mechanical force that drives a component. The ripple count circuit includes an active filter circuit and a parasitic pulse cancellation circuit. The active filter circuit is configured to filter the drive current and to generate a pulsed signal. The parasitic pulse cancelation circuit is in signal communication with the ripple count circuit to receive the pulsed signal and generates a ripple count signal that excludes parasitic pulses included in the pulsed signal having a parasitic voltage level that exceeds a voltage level of a voltage threshold. The parasitic pulse cancelation circuit actively adjusts the voltage level of the voltage threshold based at least in part on a rotational direction of the rotor.

Automated power noise susceptibility test systems are provided for one or more storage devices. A system includes a host; storage devices; and multiple noise injection modules. Each noise injection module includes: a first relay to a third relay, which are coupled to a first path or a second path. The first path includes: an operational amplifier for generating a high noise function; a first variable regulator for generating a first or second regulated power supply voltage; and a capacitor injection circuit for generating low noise function and a first power noise. The second path includes: a second variable regulator for generating a third or fourth regulated power supply voltage and a power amplifier injection circuit for generating a second power noise. The third relay selectively provides the storage device the first power noise or the second power noise.

Automated power noise susceptibility test systems are provided for one or more storage devices. A system includes a host; storage devices; and multiple noise injection modules. Each noise injection module includes: a first relay to a third relay, which are coupled to a first path or a second path. The first path includes: an operational amplifier for generating a high noise function; a first variable regulator for generating a first or second regulated power supply voltage; and a capacitor injection circuit for generating low noise function and a first power noise. The second path includes: a second variable regulator for generating a third or fourth regulated power supply voltage and a power amplifier injection circuit for generating a second power noise. The third relay selectively provides the storage device the first power noise or the second power noise.

An integrated circuit includes a first metal-insulator-semiconductor capacitor, a second metal-insulator-semiconductor capacitor, and a metal-insulator-metal capacitor. A first terminal of the first metal-insulator-semiconductor capacitor is configured to receive a first reference voltage for a higher voltage domain, while a first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second reference voltage for the higher voltage domain. A second terminal of the first metal-insulator-semiconductor capacitor is conductively connected to a first terminal of the metal-insulator-metal capacitor, while a second terminal of the second metal-insulator-semiconductor capacitor is conductively connected to a second terminal of the metal-insulator-metal capacitor. The first terminal of the metal-insulator-metal capacitor is configured to receive a first supply voltage for a lower voltage domain, and the first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second supply voltage for the lower voltage domain.

An integrated circuit includes a first metal-insulator-semiconductor capacitor, a second metal-insulator-semiconductor capacitor, and a metal-insulator-metal capacitor. A first terminal of the first metal-insulator-semiconductor capacitor is configured to receive a first reference voltage for a higher voltage domain, while a first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second reference voltage for the higher voltage domain. A second terminal of the first metal-insulator-semiconductor capacitor is conductively connected to a first terminal of the metal-insulator-metal capacitor, while a second terminal of the second metal-insulator-semiconductor capacitor is conductively connected to a second terminal of the metal-insulator-metal capacitor. The first terminal of the metal-insulator-metal capacitor is configured to receive a first supply voltage for a lower voltage domain, and the first terminal of the second metal-insulator-semiconductor capacitor is configured to receive a second supply voltage for the lower voltage domain.