A wave-generation circuit is provided. A core circuit establishes digital data. A fetch and calculation circuit generates a first data string and a second data string according to the digital data, outputs the first data string via a first pin, and outputs the second data string via a second pin. A latch circuit latches the first and second data strings. The latch circuit uses the first data string as first input data, and use the second data string as second input data. A digital-to-analog conversion circuit receives and converts the first input data and the second input data to generate a first output wave and a second output wave. After the core circuit establishes the digital data, the fetch and calculation circuit, the latch circuit, and the digital-to-analog conversion circuit operate independently of the core circuit to generate the first output wave and the second output wave.

A wave-generation circuit is provided. A core circuit establishes digital data. A fetch and calculation circuit generates a first data string and a second data string according to the digital data, outputs the first data string via a first pin, and outputs the second data string via a second pin. A latch circuit latches the first and second data strings. The latch circuit uses the first data string as first input data, and use the second data string as second input data. A digital-to-analog conversion circuit receives and converts the first input data and the second input data to generate a first output wave and a second output wave. After the core circuit establishes the digital data, the fetch and calculation circuit, the latch circuit, and the digital-to-analog conversion circuit operate independently of the core circuit to generate the first output wave and the second output wave.

A method includes performing a duty-cycle correction. The method can include inputting a signal to a duty-cycle correction circuit. The method can further include transferring the signal through an alternating current-coupling (AC-coupling) component of the duty-cycle correction circuit. The method can further include transferring the signal through a feedback circuit, wherein the feedback circuit comprises a plurality of resistors. The method can further include outputting a signal that includes a corrected duty-cycle with a particular amount of duty-cycle distortion.

A method includes performing a duty-cycle correction. The method can include inputting a signal to a duty-cycle correction circuit. The method can further include transferring the signal through an alternating current-coupling (AC-coupling) component of the duty-cycle correction circuit. The method can further include transferring the signal through a feedback circuit, wherein the feedback circuit comprises a plurality of resistors. The method can further include outputting a signal that includes a corrected duty-cycle with a particular amount of duty-cycle distortion.

An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.

An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.

A method includes performing a duty-cycle correction. The method can include inputting a signal to a duty-cycle correction circuit. The method can further include transferring the signal through an alternating current-coupling (AC-coupling) component of the duty-cycle correction circuit. The method can further include transferring the signal through a feedback circuit, wherein the feedback circuit comprises a plurality of resistors. The method can further include outputting a signal that includes a corrected duty-cycle with a particular amount of duty-cycle distortion.

A method includes performing a duty-cycle correction. The method can include inputting a signal to a duty-cycle correction circuit. The method can further include transferring the signal through an alternating current-coupling (AC-coupling) component of the duty-cycle correction circuit. The method can further include transferring the signal through a feedback circuit, wherein the feedback circuit comprises a plurality of resistors. The method can further include outputting a signal that includes a corrected duty-cycle with a particular amount of duty-cycle distortion.

A device for wireless communications can include a phase selector, a coarse delay line, and a digitally controlled edge interpolator (DCEI). The phase selector receives an input signal and is coupled to the coarse delay line. The coarse delay line can provide one of a plurality of delay ranges. A DCEI, connected to the coarse delay line can provide a fine delay output signal.

A method includes determining a phase error for a first clock signal and a second clock signal and determining an offset based on the phase error for the first clock signal and the second clock signal. The method also includes adding the offset to a phase of the first clock signal to produce a first adjusted clock signal and subtracting the offset from a phase of the second clock signal to produce a second adjusted clock signal. A phase error for the first adjusted clock signal and the second adjusted clock signal is smaller than the phase error for the first clock signal and the second clock signal.