Apparatuses and methods of DLL measurement initialization are disclosed. An example apparatus includes: a clock enable circuit that provides a first clock signal having a half frequency of an input clock signal and second clock signals having a quarter frequency of the input clock signal; a coarse delay that provides the first clock signal with a coarse delay; a fine delay that provides the first clock signal with the coarse delay and a fine delay as an output clock signal; a model delay having a feedback delay equivalent to a sum of delays of an input stage and an output stage, and provides a feedback signal that is the output clock signal with the feedback delay; and a measurement initialization circuit that performs measurement initialization. The measurement initialization circuit includes synchronizers that receive the feedback signal and the second clock signals, and provide a stop signal to the coarse delay.

A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.

A digital-to-time converter (DTC) and methods of calibrating the same reduces or mitigates nonlinearity and thus improves DTC performance. A slope of a voltage signal of the DTC is calibrated using a capacitor and a comparator. Capacitance of the capacitor and/or maximum current of a current source is adjusted to configure the comparator to output a signal during a second phase when a reference voltage signal is at or above a first level and below a second level. Calibrating gain of the DTC includes adjusting a time difference between an output signal of the DTC set at a first digital code value and the output signal of the DTC set at a second digital code value to be one period of a clock signal input to the DTC. Calibrating integral nonlinearity of the DTC includes measuring a time period for each of multiple digital code values of the DTC.

Provided is an integrated circuit. The integrated circuit includes a plurality of clock generators configured to respectively generate a plurality of clock signals, a plurality of logic circuits configured to operate in synchronization with the plurality of clock signals, and controller circuitry configured to identify meta-stability information based on frequencies of the plurality of clock signals, and configured to control at least one clock generator so that at least one of the plurality of clock signals is randomly delayed in response to the meta-stability information.

A signal sampling circuit includes the following: a signal input circuit, configured to determine a to-be-processed instruction signal and a to-be-processed chip select signal; a first instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to a first clock signal to obtain a first chip select clock signal; a second instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a second chip select clock signal; and an instruction decoding circuit, configured to perform decoding and sampling processing on the to-be-processed instruction signal according to be to-be-processed chip select signal and one of the first chip select clock signal and the second chip select clock signal to obtain a target instruction signal.

A signal sampling circuit includes the following: a signal input circuit, configured to determine a to-be-processed instruction signal and a to-be-processed chip select signal; a first instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to a first clock signal to obtain a first chip select clock signal; a second instruction sampling circuit, configured to perform two-stage sampling and logic operation processing on the to-be-processed chip select signal according to the first clock signal to obtain a second chip select clock signal; and an instruction decoding circuit, configured to perform decoding and sampling processing on the to-be-processed instruction signal according to be to-be-processed chip select signal and one of the first chip select clock signal and the second chip select clock signal to obtain a target instruction signal.

Systems and methods are disclosed for differential clock duty cycle correction. For example, a method includes converting an input rail-to-rail differential clock signal to a low-swing differential signal; fixing a DC bias level of the low-swing differential signal; changing DC bias levels of ends of the low-swing differential signal in a complementary manner to change cross-over points of the low-swing differential signal; and inputting the low-swing differential signal to a level shifter and buffer to generate a duty-corrected rail-to-rail digital differential clock signal. For example, an apparatus may include a differential pair of CMOS transmission-gate switches as clock input switches; complementary differential pairs of transistors with gate terminals connected to a differential control voltage signal; and/or extra current sources for independently controlling the DC bias voltages of ends of a differential clock signal.

Systems and methods are disclosed for differential clock duty cycle correction. For example, a method includes converting an input rail-to-rail differential clock signal to a low-swing differential signal; fixing a DC bias level of the low-swing differential signal; changing DC bias levels of ends of the low-swing differential signal in a complementary manner to change cross-over points of the low-swing differential signal; and inputting the low-swing differential signal to a level shifter and buffer to generate a duty-corrected rail-to-rail digital differential clock signal. For example, an apparatus may include a differential pair of CMOS transmission-gate switches as clock input switches; complementary differential pairs of transistors with gate terminals connected to a differential control voltage signal; and/or extra current sources for independently controlling the DC bias voltages of ends of a differential clock signal.

Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.

Disclosed herein is an apparatus that includes a data serializer including a plurality of first buffer circuits configured to receive a plurality of data, respectively, and a second buffer circuit configured to serialize the plurality of data provided from the plurality of first buffer circuits. At least one of the plurality of first buffer circuits and the second buffer circuit includes: a first circuit configured to drive a first signal node to one of first and second logic levels based on an input signal, the first circuit including a first adjustment circuit configured to adjust a driving capability of the first circuit when the first circuit drives the first signal node to the first logic level; and a second circuit configured to drive the first signal node to other of the first and second logic levels.