The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit configured to generate, under the control of a first control signal and a clock signal, first differential signals according to a signal to be compared and a first reference signal; a first positive feedback circuit configured to accelerate a difference between the first differential signals; a second sampling circuit configured to generate, under the control of a second control signal and the clock signal, second differential signals according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal; a second positive feedback circuit configured to accelerate a difference between the second differential signals.

The present disclosure provides a comparator and a decision feedback equalization circuit. The comparator includes: a first sampling circuit configured to generate, under the control of a first control signal and a clock signal, first differential signals according to a signal to be compared and a first reference signal; a first positive feedback circuit configured to accelerate a difference between the first differential signals; a second sampling circuit configured to generate, under the control of a second control signal and the clock signal, second differential signals according to the signal to be compared and a second reference signal, where the first reference signal is larger than the second reference signal; a second positive feedback circuit configured to accelerate a difference between the second differential signals.

A clock selector circuit includes a first input for receiving a reference clock signal having a reference frequency, a second input for receiving an offset clock signal having an offset frequency, a clock output for outputting the reference or offset clock signal, and switching circuitry. The switching circuitry includes a switching input and sign detector circuitry that outputs a sign signal indicating whether the reference clock signal is leading the offset clock signal in phase. In response to receiving a switching signal, the switching circuitry detects when like edges of the reference clock signal and the offset clock signal are aligned to within a predetermined tolerance, with the new signal leading the current signal if the offset frequency is lower than the reference frequency, or with the new clock signal trailing the current clock signal if not. In response, the switching circuitry switches to outputting the new clock signal.

A clock selector circuit includes a first input for receiving a reference clock signal having a reference frequency, a second input for receiving an offset clock signal having an offset frequency, a clock output for outputting the reference or offset clock signal, and switching circuitry. The switching circuitry includes a switching input and sign detector circuitry that outputs a sign signal indicating whether the reference clock signal is leading the offset clock signal in phase. In response to receiving a switching signal, the switching circuitry detects when like edges of the reference clock signal and the offset clock signal are aligned to within a predetermined tolerance, with the new signal leading the current signal if the offset frequency is lower than the reference frequency, or with the new clock signal trailing the current clock signal if not. In response, the switching circuitry switches to outputting the new clock signal.

A switching power amplifier includes logic circuitry that generates first and second components of a differential signal, based on received amplitude code and a delayed version of the same. The amplitude code includes a sign and a magnitude. When the sign is positive, a first logic path is configured to generate the first component based on the received amplitude code and the second logic path is configured to generate the second component based on the delayed amplitude code. When the sign is negative, the first logic path is configured to generate the first component based on the delayed amplitude code and the second logic path is configured to generate the second component based on the received amplitude code. The switching power amplifier further includes a differential-to-single ended conversion circuit configured to generate a single-ended signal based on the differential signal.

A multi-phase clock generator is provided in the application. The multi-phase clock generator includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes a plurality of first delay circuits. The first oscillator circuit receives the first number of multi-phase input clock signals and outputs the second number of first output clock signals, wherein the second number is larger than the first number. The second oscillator circuit is coupled to the first oscillator circuit. The second oscillator circuit includes a plurality of second delay circuits. The second oscillator circuit receives the second number of first output clock signals and outputs the second number of second output clock signals. The number of second delay circuits is less than the number of first delay circuits.

A multi-phase clock generator is provided in the application. The multi-phase clock generator includes a first oscillator circuit and a second oscillator circuit. The first oscillator circuit includes a plurality of first delay circuits. The first oscillator circuit receives the first number of multi-phase input clock signals and outputs the second number of first output clock signals, wherein the second number is larger than the first number. The second oscillator circuit is coupled to the first oscillator circuit. The second oscillator circuit includes a plurality of second delay circuits. The second oscillator circuit receives the second number of first output clock signals and outputs the second number of second output clock signals. The number of second delay circuits is less than the number of first delay circuits.

A data synthesizer includes a first input circuit, a second input circuit, and an output circuit. The first input circuit is configured to latch a first data under control of a first latch clock signal. The second input circuit is configured to latch a second data under control of the first latch clock signal. A phase of the first data is the same as a phase of the second data. The output circuit is connected to the first input circuit and the second input circuit. The output circuit is configured to output the first data and the second data in sequence.

A method executes instructions, each corresponding to switching a signal, a delay, and a condition selected among first, second, or third conditions. Each execution includes performing, after the delay, switching the signal if the condition is the first condition, if the condition is the second condition and a flag is in an active state, or if the condition is the third condition and the flag is in an inactive state, or not switching the signal if the condition is the second condition and the flag is in the inactive state, or if the condition is the third condition and the flag is in the active state. A first instruction represents a first switching of a first signal, a first delay, and the second condition, and is immediately followed by a second instruction representing the first switching of the first signal, a second delay, and the third condition.

A method executes instructions, each corresponding to switching a signal, a delay, and a condition selected among first, second, or third conditions. Each execution includes performing, after the delay, switching the signal if the condition is the first condition, if the condition is the second condition and a flag is in an active state, or if the condition is the third condition and the flag is in an inactive state, or not switching the signal if the condition is the second condition and the flag is in the inactive state, or if the condition is the third condition and the flag is in the active state. A first instruction represents a first switching of a first signal, a first delay, and the second condition, and is immediately followed by a second instruction representing the first switching of the first signal, a second delay, and the third condition.