A quadrature clock skew calibration circuit includes an I-Q clock generator having an input coupled to receive a first clock signal. The I-Q clock generator generates an in phase (I) clock signal and a quadrature (Q) clock signal. The quadrature clock skew calibration circuit includes an I-Q skew sensor having a first input coupled to receive the I clock signal and having a second input coupled to receive the Q clock signal. The I-Q skew sensor generates an I-Q skew signal responsive to a skew between the I and Q clock signals. The quadrature clock skew calibration circuit includes a control circuit having a first input coupled to receive the I-Q skew signal and having a second input coupled to receive a second clock signal. The control circuit varies the duty cycle of the first clock signal responsive to the I-Q skew signal and the second clock signal.

Circuitry and methods of operating the same to delay a signal by a precise and variable amount. One embodiment is directed to a high speed delay line used in automated test equipment. The inventors have recognized and appreciated that an input signal having high data rate may be split into parallel split signals having lower data rates that are delayed in respective parallel delay paths before being combined to generate a delayed signal. One advantage of delaying a signal in such a fashion is to provide high delay line timing accuracy at high data speeds, while using a compact circuit design using circuitry components of lower bandwidth with reduced power consumption, for example by using complementary metal-oxide-semiconductor (CMOS). A further advantage is that a high speed delay line may be constructed from multiple lower data rate parallel delay lines that are modular, simplifying circuit design.

A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

A skew control loop circuit for controlling a skew between a plurality of digital signals, and a semiconductor device, and a method of operation, for the same, may be provided. The skew control loop circuit comprises a skew detector for detecting a phase difference between the digital signals, a skew control circuit adapted for controlling an operation of the skew control loop circuit. The skew control circuit is operable in a first operating mode and in a second operating mode. The skew control loop circuit comprises also an enable input of the skew detector, wherein the enable input is adapted for receiving an enable input signal, generated by the skew control circuit, wherein the enable input is adapted for selectively enable or disable a phase detection operation of the skew detector, and wherein the enable input signal is only active during the first operating mode.

A solid state switch for connecting and disconnecting an electrical device has at least one FET-type device and at least one thyristor-type device coupled in parallel to the at least one FET-type device. A gate driver is operative to send gate drive signals to the at least one FET-type device and to the at least one thyristor-type device for providing current to the electrical device. The gate driver is constructed to control a split of the current as between the at least one FET-type device and the at least one thyristor-type device.

In a signal transmission device having a pulse generator, a RS F/F circuit and a detector, the generator generates a set pulse signal and/or a reset pulse signal when a state of a PWM signal is changed. After the generation of the set pulse signal, the generator continuously generates following pulse signals after elapse of a predetermined period of time counted from the generation of the set pulse signal. The generator adjusts, based on a selector signal, the predetermined period of time counted to a time when the following pulse signal is transmitted at a first time. The detector detects the state of the selector signal based on the predetermined period of time counted from a time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to a time when receiving the following pulse signal at a first time.

In a signal transmission device having a pulse generator, a RS F/F circuit and a detector, the generator generates a set pulse signal and/or a reset pulse signal when a state of a PWM signal is changed. After the generation of the set pulse signal, the generator continuously generates following pulse signals after elapse of a predetermined period of time counted from the generation of the set pulse signal. The generator adjusts, based on a selector signal, the predetermined period of time counted to a time when the following pulse signal is transmitted at a first time. The detector detects the state of the selector signal based on the predetermined period of time counted from a time when the RS F/F circuit receives the set pulse signal or the reset pulse signal to a time when receiving the following pulse signal at a first time.

A repeater circuit includes at least a first input, and output, and a repeater. The first input for receiving a single-ended data signal from an embedded universal serial bus (eUSB) host. The output provides a differential data signal in a differential universal serial bus (USB) format. The repeater is coupled between the first input and output for converting the single-ended data signal to a differential data signal, the repeater includes an adaptive delay element operable for both sides of the differential data signal to delay one, but not both, of a rising edge and a falling edge of the differential data signal in order to meet a crossover specification for the USB format.

A time amplifier includes a first signal regeneration circuit, a second signal regeneration circuit, a first delay circuit configured to receive the second input signal and output the delayed second input signal by a predetermined delay time, and a second delay circuit configured to receive the first input signal and output the delayed first input signal by the predetermined delay time. A corresponding signal regeneration operation is stopped when at least one of the first and second output signals is high. The at least one output signal remains high.

Methods and systems for timing analysis and closure during logic synthesis of synchronous digital circuitry are provided, which may be used to prevent timing conflicts in logic designs that may have data transfers between regions with substantial clock skew. In programmable logic devices having hardened circuitry and programmable fabric, data transfers between memory elements in hardened circuitry and programmable fabric may be subject to substantial clock skews and unknown latencies. Embodiments may employ pre-calculated latencies that may be stored in a file and/or a database, and dynamically retrieved during timing synthesis to determine multicycle constraints to mitigate latencies. Embodiments may employ destination multicycle constraints, which use as reference the clock waveforms delayed due to latency.