Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths between a signal source, such as a driver, and a load. The paths may have different lengths, thus causing delay mismatches. An exemplary circuit of the type described herein may comprise delay elements and at least one feedback circuit designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load.

Circuits and methods for delay mismatch compensation are described. A circuit may comprise multiple data paths between a signal source, such as a driver, and a load. The paths may have different lengths, thus causing delay mismatches. An exemplary circuit of the type described herein may comprise delay elements and at least one feedback circuit designed to compensate for such delay mismatches. The circuit may operate in different phases, such as a compensation phase and a driving phase. In the compensation phase, rings oscillators including delay elements and the at least one feedback circuit may be formed. In this phase the delay may be adjusted to compensate for mismatches. In the driving phase, the signal source may be connected to the load.

A phase interpolator is provided. The phase interpolator includes a plurality of first interpolation cells each configured to supply a first current to a common node of the phase interpolator. Further, the phase interpolator includes a plurality of second interpolation cells each configured to supply a second current to the common node. The second current is lower than the first current, wherein a sum of the plurality of second currents supplied to the common node by the plurality of second interpolation cells is substantially equal to the first current.

A phase rotator receives control signals and thermometer coded signals that specifies the phase of an output signal. The phase rotator may be used, for example, by a clock and data recovery (CDR) circuit to continually rotate the phase of a clock to compensate for phase/frequency mismatches between received data and the clock. The control signals determine the phase quadrant (i.e., 0°-90°, 90°-180°, etc.) of the output signal. The thermometer coded signals determine the phase of the output signal within a quadrant by steering a set of bias currents between two or more nodes. The set of bias currents are selected to reduce the non-linearity between the thermometer coded value and the phase of the output signal.

An electronic device includes: a first equalizing circuit configured to receive a data signal and output a first equalizing signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalizing circuit configured to output a second equalizing signal based on the first pulse signal and the second pulse signal that have been inverted; and an output terminal configured to output an output signal in which the first equalizing signal and the second equalizing signal have been summed.

An electronic device includes: a first equalizing circuit configured to receive a data signal and output a first equalizing signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalizing circuit configured to output a second equalizing signal based on the first pulse signal and the second pulse signal that have been inverted; and an output terminal configured to output an output signal in which the first equalizing signal and the second equalizing signal have been summed.

A device and method for controllably delaying an electrical signal includes a first signal transfer path between a signal input and a signal output. The first signal transfer path includes a first signal transfer stage with a first differential pair and a common, adjustable first quiescent current source, and a second signal transfer path between the signal input and the signal output. The second signal transfer path includes a second signal transfer stage with a second differential pair and a common, adjustable second quiescent current source. An internal delay stage is arranged between the signal input and the second signal transfer stage and has a third differential pair and a common, adjustable third quiescent current source, and signal combination stage for additively superimposing the electrical signal transferred via the first signal transfer path on to the electrical signal transferred via the second signal transfer path.

A device and method for controllably delaying an electrical signal includes a first signal transfer path between a signal input and a signal output. The first signal transfer path includes a first signal transfer stage with a first differential pair and a common, adjustable first quiescent current source, and a second signal transfer path between the signal input and the signal output. The second signal transfer path includes a second signal transfer stage with a second differential pair and a common, adjustable second quiescent current source. An internal delay stage is arranged between the signal input and the second signal transfer stage and has a third differential pair and a common, adjustable third quiescent current source, and signal combination stage for additively superimposing the electrical signal transferred via the first signal transfer path on to the electrical signal transferred via the second signal transfer path.

The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over ()}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over ()}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over ()}n phase signal in a first mode. The controller is further configured to provide the mode input of each of 2{circumflex over ()}(n1) odd stages with a first steady state signal and the mode input of each of 2{circumflex over ()}(n1) even stages with a second steady state signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with the same periodic binary signal as in the first mode to cause either the 2{circumflex over ()}(n1) odd stages or the 2{circumflex over ()}(n1) even stages to collectively generate a 2{circumflex over ()}(n1) phase signal in a second mode.

The disclosure relates to technology for generating multi-phase signals. An apparatus includes 2{circumflex over ()}n phase signal generation stages. The apparatus also includes a controller configured to provide a mode input of each of the 2{circumflex over ()}n stages with an active periodic binary signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with another periodic binary signal to collectively generate a 2{circumflex over ()}n phase signal in a first mode. The controller is further configured to provide the mode input of each of 2{circumflex over ()}(n1) odd stages with a first steady state signal and the mode input of each of 2{circumflex over ()}(n1) even stages with a second steady state signal with remaining inputs of each of the 2{circumflex over ()}n stages provided with the same periodic binary signal as in the first mode to cause either the 2{circumflex over ()}(n1) odd stages or the 2{circumflex over ()}(n1) even stages to collectively generate a 2{circumflex over ()}(n1) phase signal in a second mode.