Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to induce symmetry in the first and second phase clock signals such that durational midpoints of overlapping opposite phases of the first and second phase clock signals are substantially aligned.

Aspects of the disclosure are directed to quadrature clock generation with injection locking. In accordance with one aspect, quadrature clock generation with injection locking uses a digital calibration circuit having a coarse calibration circuit and a fine calibration circuit to perform a coarse frequency calibration of a controlled oscillator, wherein the controlled oscillator is coupled to the digital calibration circuit; characterize a replica oscillator signal path associated with an oscillator replica circuit, wherein the oscillator replica circuit is coupled to the controlled oscillator; perform a fine frequency calibration of the controlled oscillator by measuring a phase difference between the controlled oscillator and the oscillator replica circuit; and generate a calibrated set of quadrature clock signals after performing the fine frequency calibration of the controlled oscillator.

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

A semiconductor apparatus includes a pulse generation circuit which generates a pulse signal in response to a clock, and an amplification circuit which generates an output signal in response to an input signal, the clock, and the pulse signal, wherein the amplification circuit voltage is configured to amplify a voltage level difference between a pair of latch input nodes.

An output circuit includes: a first node to which a first voltage is applied; a second node to which a second voltage is applied; a regulator which outputs the second voltage to the second node based on the first voltage applied to the first node; a pre-driver to which a first signal is input and which operates based on the second voltage; and an output driver to which a signal from the pre-driver is input and which outputs a second signal. The regulator short-circuits the first node and the second node while the pre-driver is in a standby state, and controls the second voltage to be different from the first voltage after the pre-driver transitions from the standby state to a normal operation state.

A clock generation circuit includes: a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to induce symmetry in the first and second phase clock signals such that durational midpoints of overlapping opposite phases of the first and second phase clock signals are substantially aligned.

In order to prevent or at least reduce parasitic capacitive loads at a device (200) for controllably delaying an electrical signal, the device comprising a first signal transfer path (207) between a signal input (201) and a signal output (204), the first signal transfer path (207) comprising a first signal transfer stage (208) with a first differential pair (209) and a common, adjustable first quiescent current source (212), a second signal transfer path (213) between the signal input (201) and the signal output (204), the second signal transfer path (213) comprising a second signal transfer stage (214) with a second differential pair (215) and a common, adjustable second quiescent current source (218), and an internal delay stage (219), arranged between the signal input (201) and the second signal transfer stage (214) and having a third differential pair (220) and a common, adjustable third quiescent current source (223), and a signal combination stage (224) for additively superimposing the electrical signal transferred via the first signal transfer path (207) on to the electrical signal transferred via the second signal transfer path (213),
at least one current modulation stage (235, 236) for adjusting the quiescent current of at least one of the first and/or second and/or third quiescent current source (212, 218, 223) is proposed.

A corresponding method for controlling the delay of an electrical signal and for said delaying the electrical signal is also proposed.