An apparatus includes a voltage divider circuit including a plurality of series- connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.

An apparatus includes a voltage divider circuit including a plurality of series- connected capacitors and including an input terminal of one of the capacitors configured to receive a first voltage from a switch, and a ring node comprising the connection between at least two of the series-connected capacitors. The apparatus further includes a negative clamp circuit coupled to the ring node of the voltage divider circuit and a bias voltage node. The bias voltage node is configured to receive a bias voltage and responsive to a ring voltage on the ring node being less than the bias voltage, the negative clamp circuit is configured to clamp the ring voltage at a first threshold voltage. The apparatus also includes a peak detector circuit coupled to the ring node of the voltage divider circuit and configured to detect a peak amplitude of the ring voltage. The apparatus further includes a switch driver coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak amplitude.

An apparatus to monitor and control a switching rate in a switch includes a differentiator circuit including a capacitor and a configurable resistor. The differentiator circuit further includes an input terminal of the capacitors configured to receive a first voltage from a switch and a differentiator node configured to receive a differentiated voltage based on the first voltage. The apparatus includes a peak detector circuit coupled to the differentiator node and configured to detect a peak value of the differentiated voltage. The apparatus further includes a driver circuit coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak value of the differentiated voltage.

An apparatus to monitor and control a switching rate in a switch includes a differentiator circuit including a capacitor and a configurable resistor. The differentiator circuit further includes an input terminal of the capacitors configured to receive a first voltage from a switch and a differentiator node configured to receive a differentiated voltage based on the first voltage. The apparatus includes a peak detector circuit coupled to the differentiator node and configured to detect a peak value of the differentiated voltage. The apparatus further includes a driver circuit coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak value of the differentiated voltage.

A peak detector including an input circuit with five same-sized transistors, in which four of the input transistors are coupled in parallel between a control node and a bias node and receive a corresponding one of two in-phase signals and two quadrature signals. The fifth transistor is coupled between a current node and the bias node and has its control terminal coupled to an output node. A bias circuit establishes a predetermined bias current that flows through the five input transistors. A current mirror mirrors the current through the fifth transistor from the current terminal into the four parallel-coupled input transistors via the control node. An output circuit charges a peak capacitor based on voltage developed at the control terminal of the fifth transistor. The peak detector is low power and compact and detects the actual peak of the input signal with greater accuracy compared to a conventional peak detector.

A peak detector including an input circuit with five same-sized transistors, in which four of the input transistors are coupled in parallel between a control node and a bias node and receive a corresponding one of two in-phase signals and two quadrature signals. The fifth transistor is coupled between a current node and the bias node and has its control terminal coupled to an output node. A bias circuit establishes a predetermined bias current that flows through the five input transistors. A current mirror mirrors the current through the fifth transistor from the current terminal into the four parallel-coupled input transistors via the control node. An output circuit charges a peak capacitor based on voltage developed at the control terminal of the fifth transistor. The peak detector is low power and compact and detects the actual peak of the input signal with greater accuracy compared to a conventional peak detector.

The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.

The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.

A ringing peak detector module detects a ringing at the output of an inductive load driver including a bridge circuit containing high side and low side switches. A ringing peak detector receives differential feedback signals representative of the drain-source voltage of the low-side switch and detects a ringing peak of an oscillation of a current/voltage on the inductive load. A module compares said detected ringing peak with a maximum value and controls said driver by an error signal calculated as a function of the difference between said peak value and maximum value. The ringing peak detector module includes an input buffer module upstream of said peak detector circuit that shifts the differential feedback signals so a common mode of these signals is centered at a half-dynamic level of a supply voltage to provide correspondingly shifted voltages forming a shifted differential output corresponding to a steady state of the differential feedback signals.

A ringing peak detector module detects a ringing at the output of an inductive load driver including a bridge circuit containing high side and low side switches. A ringing peak detector receives differential feedback signals representative of the drain-source voltage of the low-side switch and detects a ringing peak of an oscillation of a current/voltage on the inductive load. A module compares said detected ringing peak with a maximum value and controls said driver by an error signal calculated as a function of the difference between said peak value and maximum value. The ringing peak detector module includes an input buffer module upstream of said peak detector circuit that shifts the differential feedback signals so a common mode of these signals is centered at a half-dynamic level of a supply voltage to provide correspondingly shifted voltages forming a shifted differential output corresponding to a steady state of the differential feedback signals.