A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs. For each and every unique combination of two of the multiple inputs, the voltage selection circuit may include an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs and the output; a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs through the channel of a depletion mode FET; an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the two inputs and the output; and a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs through the channel of an additional depletion mode FET.

A maximum voltage selection circuit may include multiple inputs, each for receiving a different input voltage, an output for delivering the highest of the input voltages, and a voltage selection circuit. The voltage selection circuit may automatically select the input having the largest voltage magnitude, automatically deliver the voltage at the selected input to the output, and not draw quiescent operating current from any of the inputs. For each and every unique combination of two of the multiple inputs, the voltage selection circuit may include an enhancement mode FET with a channel connected in series between a first input of the unique combination of the two inputs and the output; a connection between the gate of the enhancement mode FET and the second input of the unique combination of the two inputs through the channel of a depletion mode FET; an additional enhancement mode FET with a channel connected in series between the second of the unique combination of the two inputs and the output; and a connection between the gate of the additional enhancement mode FET and the first of the unique combination of the two inputs through the channel of an additional depletion mode FET.

A power supply includes a power switch and a switch control circuit controlling a switching operation of the power switch using a comparison voltage generated according to an output, determining a clamping voltage by sensing an input voltage during a start-up period, and clamping the comparison voltage to the clamping voltage during the start-up period.

A power supply includes a power switch and a switch control circuit controlling a switching operation of the power switch using a comparison voltage generated according to an output, determining a clamping voltage by sensing an input voltage during a start-up period, and clamping the comparison voltage to the clamping voltage during the start-up period.

A peak detector using a charge pump is provided. The peak detector includes a differential amplifier configured to receive an input signal to be detected through an input node and amplify the received signal; a current control logic configured to create two or more current control signals by comparing a signal output from the differential amplifier with two or more reference voltages; a mirror current source portion comprising two or more mirror current sources configured to be driven respectively by the current control signals from the current control logic; a capacitor configured to be charged or discharged by currents output from the mirror current sources; and a reset circuit configured to reset a voltage of the capacitor.

A peak detector using a charge pump is provided. The peak detector includes a differential amplifier configured to receive an input signal to be detected through an input node and amplify the received signal; a current control logic configured to create two or more current control signals by comparing a signal output from the differential amplifier with two or more reference voltages; a mirror current source portion comprising two or more mirror current sources configured to be driven respectively by the current control signals from the current control logic; a capacitor configured to be charged or discharged by currents output from the mirror current sources; and a reset circuit configured to reset a voltage of the capacitor.

Embodiments of the disclosure provide a peak voltage detection circuit with reduced charge loss. A circuit structure of the disclosure includes a peak voltage detector having a first input node coupled to an input line and a second input node coupled to a first electrically actuated switch. The peak voltage detector coupling the first input node and the second input node to an output node, and a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor. The first electrically actuated switch couples the capacitor to the second input node of the peak voltage detector. The input line is coupled to a control node of the first electrically actuated switch and a control node of the second electrically actuated switch.

The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.

The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.

A semiconductor device may include: a variable delay circuit configured to delay a data strobe signal according to a delay control signal and output a delayed data strobe signal; a data sampler configured to compare a level of a reference voltage and a value of a data signal in synchronization with the delayed data strobe signal, and determine a logic level of the value of the data signal, the data signal having a training pattern; and a control circuit configured to determine a delay amount of the data strobe signal and generate the delay control signal and the reference voltage according to an output signal of the data sampler.