A system and method are described herein for gating at least one input to an amplifier, the method comprising: measuring at least one audio analog signal level received by the amplifier at a first input; determining whether the received at least one audio analog signal level is below a predetermined threshold level; and gating the first input such that the received audio analog signal level is ignored in further processing by the amplifier.

A system and method are described herein for gating at least one input to an amplifier, the method comprising: measuring at least one audio analog signal level received by the amplifier at a first input; determining whether the received at least one audio analog signal level is below a predetermined threshold level; and gating the first input such that the received audio analog signal level is ignored in further processing by the amplifier.

Described herein is a system and method for generating text caption information for an audio-video (AV) signal, the systems and method comprising: receiving an AV signal; extracting audio from the AV signal to form an extracted audio signal; time stamping both the extracted audio signal and the received AV signal; partitioning the extracted audio signal into a first predetermined duration segment of extracted audio signal; generating text captions from the partitioned extracted audio signal over a first duration, and converting the same to a video text signal, with the same time stamp as the extracted audio signal and received AV signal; delaying the received AV signal by an amount of time substantially similar to the first duration; combining the time stamped video text signal and the delayed time stamped received AV signal based on the time stamps; and outputting the combined time stamped video text signal and the time stamped received AV signal to a display.

A system and method are disclosed herein for automatically adjusting an output level of audio in an audio playback network, the method comprising: selecting an audio source to be received into, and output from, an audio playback network; setting a broadcast output volume level of the selected audio source; receiving new audio from any one of a plurality of audio sources, and broadcasting the new audio from one or more loudspeakers; substantially continuously measuring a volume level of the broadcast new audio; and correcting the broadcast new audio to match the set broadcast output volume level.

A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.

A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.

A peak detector including an input transistor, an isolation transistor, at least one load transistor, a buffer, a control transistor, a current source and at least one resistor. The isolation transistor isolates the input and load transistors from the supply voltage for power supply rejection. The buffer, control transistor, current source and resistor(s) bias the input transistor to remain in a saturation region and each load transistor to remain in a triode region. The buffer may be a unity gain buffer. The control transistor may match each load transistor with matching threshold voltages. An input bias circuit may be included to bias an input node to a direct-current voltage. The load transistor(s) may be biased to have so that the output voltage is proportional to a peak voltage of the input node. The peak detector may be configured to detect multiple inputs and may have shared circuitry.

A peak detector including an input transistor, an isolation transistor, at least one load transistor, a buffer, a control transistor, a current source and at least one resistor. The isolation transistor isolates the input and load transistors from the supply voltage for power supply rejection. The buffer, control transistor, current source and resistor(s) bias the input transistor to remain in a saturation region and each load transistor to remain in a triode region. The buffer may be a unity gain buffer. The control transistor may match each load transistor with matching threshold voltages. An input bias circuit may be included to bias an input node to a direct-current voltage. The load transistor(s) may be biased to have so that the output voltage is proportional to a peak voltage of the input node. The peak detector may be configured to detect multiple inputs and may have shared circuitry.

An apparatus and method for current peak detection. The apparatus includes a pulse laser diode array, a sense resistor, a capacitive voltage divider (CVD) electrically coupled to the pulse laser diode array, a first current rectifier, a second current rectifier, a first current peak detector, a second current peak detector, an analog-to-digital converter (ADC) operable to convert the analog outputs from each current peak detector to a digital output signal, and a digital signal processing (DSP) unit operable to detect, from the digital output signal, a current peak pulse at the top and the bottom of the sense resistor.

The transition to a horizontal integrated circuit (IC) design flow has raised concerns regarding the security and protection of IC intellectual property (IP). Obfuscation of an IC has been explored as a potential methodology to protect IP in both the digital and analog domains in isolation. However, novel methods are required for analog mixed-signal circuits that both enhance the current disjoint implementations of analog and digital security measures and prevent an independent adversarial attack of each domain. A methodology generates functional and behavioral dependencies between the analog and digital domains that results in an increase in the adversarial key search space. The dependencies between the analog and digital keys result in a 3× increase in the number of iterations required to complete the SAT attack.