An electronic device includes: a first equalizing circuit configured to receive a data signal and output a first equalizing signal based on the data signal; a pulse generator configured to generate a first pulse signal and a second pulse signal in response to a rising edge and a falling edge of the data signal, respectively; a second equalizing circuit configured to output a second equalizing signal based on the first pulse signal and the second pulse signal that have been inverted; and an output terminal configured to output an output signal in which the first equalizing signal and the second equalizing signal have been summed.

A combining network for an array of SPAD devices includes: synchronous sampling circuits, wherein each synchronous sampling circuit is coupled to an output of a corresponding SPAD device and is configured to generate a pulse or an edge each time an event is detected; and a summation circuit coupled to an output of each of the synchronous sampling circuits and configured to count a number of pulses or edges to generate a binary output value.

The invention relates to a filter unit for filtering multiple pulse signals comprising a number of filter circuits, which are connected in parallel. Each filter circuit comprises an input and an output, wherein the input is configured to receive an amplitude of an input signal and the output is configured to activate an output signal. Each filter circuit has an allocated filter level and further comprises a pulse level detection circuit configured to detect a change of state of a pulse level of the input signal. The change of state comprises a transition from a first pulse level to a second pulse level and if the pulse level corresponds to the allocated filter level of the filter circuit the output of said filter circuit is activated.

A clock detecting circuit is provided. The clock detecting circuit includes a first clock converting circuit, a second clock converting circuit and a frequency comparator. The first clock converting circuit converts an internal clock to a first clock. The second clock converting circuit converts an external clock to a second clock. The frequency comparator generates a first edge clock in response the first clock and generates a second edge clock in response the second clock. The frequency comparator generates a first sensing voltage in response to a plurality of positive pulses of the first edge clock and generate a second sensing voltage in response to a plurality of positive pulses of the second edge clock. The frequency comparator compares the first sensing voltage and the second sensing voltage to provide a frequency comparing result between the external clock and the internal clock.

A clock detecting circuit is provided. The clock detecting circuit includes a first clock converting circuit, a second clock converting circuit and a frequency comparator. The first clock converting circuit converts an internal clock to a first clock. The second clock converting circuit converts an external clock to a second clock. The frequency comparator generates a first edge clock in response the first clock and generates a second edge clock in response the second clock. The frequency comparator generates a first sensing voltage in response to a plurality of positive pulses of the first edge clock and generate a second sensing voltage in response to a plurality of positive pulses of the second edge clock. The frequency comparator compares the first sensing voltage and the second sensing voltage to provide a frequency comparing result between the external clock and the internal clock.

Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

Methods, apparatus, systems, and articles of manufacture are disclosed for cross-conduction detection. An example apparatus includes a cross detector circuit including a first transistor and a second transistor, the first transistor coupled to a load, a third transistor coupled to a first controlled delay circuit and the first transistor, a fourth transistor coupled to a second controlled delay circuit and to the third transistor at a phase node, and a control circuit coupled to the first controlled delay circuit, the second controlled delay circuit, and the load.

A system for driving a transducer having a plurality of coils, the system comprising: a modulator for outputting a digital output signal representative of a received analogue input signal at a modulator output; a clock controlled delay element for applying a delay to the digital output signal to generate a first delayed signal at a delay element output; wherein the modulator output is couplable to a first coil of the plurality of the coils of the transducer and the delay element output is couplable to a second coil of the plurality of coils of the transducer.

A system for driving a transducer having a plurality of coils, the system comprising: a modulator for outputting a digital output signal representative of a received analogue input signal at a modulator output; a clock controlled delay element for applying a delay to the digital output signal to generate a first delayed signal at a delay element output; wherein the modulator output is couplable to a first coil of the plurality of the coils of the transducer and the delay element output is couplable to a second coil of the plurality of coils of the transducer.

A delay measurement circuit includes a first skew circuit disposed proximate to a first bonding pad configured to receive a first clock signal having a first frequency. The delay measurement circuit includes a second skew circuit disposed proximate to a second bonding pad configured to receive a second clock signal having a second frequency. The first and second skew circuits each have a first mode of operation as zero-delay-return path and a second mode of operation as a synchronized pass path. The delay measurement circuit includes a pair of conductive traces coupled to the first skew circuit, another pair of conductive traces coupled to the second skew circuit, a time-to-digital converter circuit, and a switch circuit configured to selectively couple the time-to-digital converter circuit to the first skew circuit via the pair of conductive traces and the second skew circuit via the other pair of conductive traces.