A method for controlling a load-current zero-crossing of a switching regulator having a high-side switch and a low-side switch includes detecting, by a spike detection circuit, a presence of a spike on an output voltage of the switching regulator, determining, by the spike detection circuit, in the event that a spike is present, whether the spike is a positive spike or a negative spike, and adjusting a turn-off timing of the low-side switch based on a determination result.

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

An apparatus includes a first half-cell, a second half cell and a multiplexer. The first half-cell may comprise a first input stage configured to present a first input signal to a first auto-zero stage. The second half-cell may comprise a second input stage configured to present a second input signal to a second auto-zero stage. The multiplexer may receive a first output from the first auto-zero stage, receive a second output from the second auto-zero stage and present one of the first output and the second output. The first half-cell and the second half-cell may implement a capacitive coupling. The capacitive coupling may provide a rail-to-rail common-mode input range. The first half-cell and the second half-cell may prevent a mismatch between data signals and clock signals. The first half-cell and the second half-cell may each be configured to implement a calibration when idle.

A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed. The circuit for detecting current zero-crossing point includes: a load power supply circuit (14), a voltage-dividing resistor (16), a transistor switch (15), a zero-crossing detection circuit (19); the load power supply circuit (14) includes: a load (11), a diode (13), and an inductor (12); one end of the load power supply circuit (14) is connected with the operating voltage input terminal, the other end of the load power supply circuit (14) is connected with a first end of the transistor switch (15) and a first end of the voltage-dividing resistor (16), a second end of the voltage-dividing resistor (16) and a second end of the transistor switch (15) are connected with the ground, the load voltage is controlled by the transistor switch (15), the voltage-dividing terminal of the voltage-dividing resistor (16) is connected to a signal input terminal of the zero-crossing detection circuit (19), the zero-crossing detection circuit (19) is used to determine whether the current of the diode (13) crosses zero to obtain the on time of the diode (13), and the circuit for detecting load voltage uses the on time of the diode (13) and the on time of the transistor switch (15) to obtain the load voltage. The circuits are simple, but with high detection efficiency and low cost.

A circuit and a method for detecting a current zero-crossing point, and a circuit and method for detecting a load voltage are disclosed. The circuit for detecting current zero-crossing point includes: a load power supply circuit (14), a voltage-dividing resistor (16), a transistor switch (15), a zero-crossing detection circuit (19); the load power supply circuit (14) includes: a load (11), a diode (13), and an inductor (12); one end of the load power supply circuit (14) is connected with the operating voltage input terminal, the other end of the load power supply circuit (14) is connected with a first end of the transistor switch (15) and a first end of the voltage-dividing resistor (16), a second end of the voltage-dividing resistor (16) and a second end of the transistor switch (15) are connected with the ground, the load voltage is controlled by the transistor switch (15), the voltage-dividing terminal of the voltage-dividing resistor (16) is connected to a signal input terminal of the zero-crossing detection circuit (19), the zero-crossing detection circuit (19) is used to determine whether the current of the diode (13) crosses zero to obtain the on time of the diode (13), and the circuit for detecting load voltage uses the on time of the diode (13) and the on time of the transistor switch (15) to obtain the load voltage. The circuits are simple, but with high detection efficiency and low cost.

A zero detection circuit includes a chain of masked OR circuits. Each masked OR circuit includes data inputs. Each data input is configured to receive a respective data input bit. Each masked OR circuit further includes an input mask input to receive one or more input masking bits, an output mask input to receive an output masking bit and a data output. The zero detection circuit is configured to output a bit equal to an OR combination, masked with the output masking bit, of the data input bits, each demasked with an input masking bit of the one or more input masking bits. One of the inputs of each masked OR circuit except the first masked OR circuit of the chain of masked OR circuits is coupled to the data output of the masked OR circuit preceding the masked OR circuit in the chain of masked OR circuits.

A zero detection circuit includes a chain of masked OR circuits. Each masked OR circuit includes data inputs. Each data input is configured to receive a respective data input bit. Each masked OR circuit further includes an input mask input to receive one or more input masking bits, an output mask input to receive an output masking bit and a data output. The zero detection circuit is configured to output a bit equal to an OR combination, masked with the output masking bit, of the data input bits, each demasked with an input masking bit of the one or more input masking bits. One of the inputs of each masked OR circuit except the first masked OR circuit of the chain of masked OR circuits is coupled to the data output of the masked OR circuit preceding the masked OR circuit in the chain of masked OR circuits.

Methods and apparatus for detecting zero-volt crossing in a field-effect transistor. A comparator compares a drain-to source voltage of the transistor to a threshold voltage. A gate voltage signal of the transistor is provided to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator. A control function with respect to the transistor is performed based on the value of the comparator output.

Methods and apparatus for detecting zero-volt crossing in a field-effect transistor. A comparator compares a drain-to source voltage of the transistor to a threshold voltage. A gate voltage signal of the transistor is provided to a clock input of the comparator such that said gate voltage signal is used to latch a result of said comparison to an output of the comparator. A control function with respect to the transistor is performed based on the value of the comparator output.

A rotor position detection system according to one embodiment includes a H bridge circuit, a current detection circuit, a time measurement circuit, a zero cross determination circuit, and a rotor position calculation circuit. The zero cross determination circuit calculates a zero cross position of the induced voltage of the motor based on a difference time calculated by the time measurement circuit. The rotor position calculation circuit calculates a rotor position of the motor based on the zero cross position of the induced voltage.