Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry and zero crossing logic circuitry. The switch controller circuitry is to control a conduction state of a high side switch and a low side switch in a DC to DC converter. The zero crossing logic circuitry includes phase comparator circuitry, a first clocking circuitry and a second clocking circuitry. Each clocking circuitry includes one or more delay elements. The zero crossing logic circuitry is to monitor a switch node voltage, Vsw, and to determine whether Vsw is greater than a reference, Vref. The switch controller circuitry is to turn off a low side switch if Vsw is greater than Vref while the low side switch is turned on, Vsw greater than Vref corresponding to a negative inductor current.

A technique for detecting a valley timing at lower cost is described. A drive circuit comprises a peak voltage holder, a valley voltage holder, a center voltage generator, a monitor, and a detector. The peak voltage holder holds a peak voltage of an oscillating signal that is based on a voltage at a terminal of an inductor coupled to a switching element. The valley voltage holder holds a valley voltage of the oscillating signal. The center voltage generator generates a center voltage based on the peak voltage and the valley voltage. The monitor monitors the present value of the voltage at the terminal. The detector detects, as a valley timing, a timing at which a predetermined delay time has elapsed from a timing at which the monitored present value of the voltage at the terminal has fallen below the center voltage.

A technique for detecting a valley timing at lower cost is described. A drive circuit comprises a peak voltage holder, a valley voltage holder, a center voltage generator, a monitor, and a detector. The peak voltage holder holds a peak voltage of an oscillating signal that is based on a voltage at a terminal of an inductor coupled to a switching element. The valley voltage holder holds a valley voltage of the oscillating signal. The center voltage generator generates a center voltage based on the peak voltage and the valley voltage. The monitor monitors the present value of the voltage at the terminal. The detector detects, as a valley timing, a timing at which a predetermined delay time has elapsed from a timing at which the monitored present value of the voltage at the terminal has fallen below the center voltage.

An electronic circuit for amplifying signals with two components in phase quadrature, which includes: a feedback amplifier with a feedback capacitor; a switch that drives charging and discharging of the feedback capacitor; an additional capacitor; and a coupling circuit, which alternatively connects the additional capacitor in parallel to the feedback capacitor or else decouples the additional capacitor from the feedback capacitor. The switch opens at a first instant, where a first one of the two components assumes a first zero value; the coupling circuit decouples the additional capacitor from the feedback capacitor in a way synchronous with a second instant, where the first component assumes a second zero value.

An electronic circuit for amplifying signals with two components in phase quadrature, which includes: a feedback amplifier with a feedback capacitor; a switch that drives charging and discharging of the feedback capacitor; an additional capacitor; and a coupling circuit, which alternatively connects the additional capacitor in parallel to the feedback capacitor or else decouples the additional capacitor from the feedback capacitor. The switch opens at a first instant, where a first one of the two components assumes a first zero value; the coupling circuit decouples the additional capacitor from the feedback capacitor in a way synchronous with a second instant, where the first component assumes a second zero value.

Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry and zero crossing logic circuitry. The switch controller circuitry is to control a conduction state of a high side switch and a low side switch in a DC to DC converter. The zero crossing logic circuitry includes phase comparator circuitry, a first clocking circuitry and a second clocking circuitry. Each clocking circuitry includes one or more delay elements. The zero crossing logic circuitry is to monitor a switch node voltage, Vsw, and to determine whether Vsw is greater than a reference, Vref. The switch controller circuitry is to turn off a low side switch if Vsw is greater than Vref while the low side switch is turned on, Vsw greater than Vref corresponding to a negative inductor current.

A power converter includes a first bus converter for converting a first direct current (DC) bus voltage into a first high frequency alternating current (AC) voltage and a second bus converter for converting a second high frequency AC voltage into a second DC bus voltage. A resonant circuit couples the first bus converter and the second bus converter. Further, a controller provides switching signals to the first bus converter and the second bus converter to operate the power converter in a soft switching mode. The controller includes a voltage detection circuit connected across at least one switching device of the power converter to detect a device voltage across the at least one switching device and a counter to count a number of hard switching detection pulses of the hard switching pulse signal detector. The controller also includes a calculation module to update the number of hard switching detection pulses of the hard switching instances and to generate a new number of hard switching detection pulses and a comparator to compare the new number of hard switching detection pulses with a threshold value and to provide a control signal if the new number exceeds the threshold value.

A symmetry control circuit for a trailing edge phase control dimmer circuit for controlling alternating current (AC) power to a load, the symmetry control circuit including: a bias signal generator circuit configured to monitor non-conduction periods of each half cycle of said AC power for an elapsed duration of the non-conduction periods, and generate a bias signal voltage based on the elapsed duration, whereby an amplitude of the bias signal voltage is proportional to the elapsed duration of the non-conduction periods; and a bias signal converter circuit configured to convert the bias signal voltage to a bias signal current, wherein the bias signal current is added to a reference current of a conduction period timing circuit configured to determine said conduction periods, and wherein the conduction period timing circuit is configured to alter one of the conduction periods immediately following one of the non-conduction periods based on the bias signal current when added to the reference current to compensate for a phase shift of a zero-crossing of said one of the non-conduction periods corresponding to an elapsed duration of said one of the non-conduction periods so as to restore symmetry of the non-conduction periods of each half cycle of AC power.

A zero-crossing detection circuit for a trailing edge phase control dimmer circuit for controlling alternating current (AC) power to a load, wherein the circuit includes: a switching circuit for controlling delivery of AC power to the load by conducting power to the load in an ON state and not conducting power to the load in an OFF state; a switching control circuit for controlling turn-OFF and turn-ON of the switching circuit at each cycle of the AC; and a rectifier for rectifying the AC power in the non-conduction period to generate rectified dimmer voltage to be provided to the dimmer circuit, wherein the zero-crossing detection circuit includes a current sink circuit; wherein the current sink circuit has a low impedance at low instantaneous AC voltages; a comparator circuit configured to detect zero crossings of a first threshold value of the rectified dimmer voltage.

A technique for detecting a valley timing at lower cost is described. A drive circuit comprises a peak voltage holder, a valley voltage holder, a center voltage generator, a monitor, and a detector. The peak voltage holder holds a peak voltage of an oscillating signal that is based on a voltage at a terminal of an inductor coupled to a switching element. The valley voltage holder holds a valley voltage of the oscillating signal. The center voltage generator generates a center voltage based on the peak voltage and the valley voltage. The monitor monitors the present value of the voltage at the terminal. The detector detects, as a valley timing, a timing at which a predetermined delay time has elapsed from a timing at which the monitored present value of the voltage at the terminal has fallen below the center voltage.