A low latency comparator circuit with a local clock circuit is disclosed. A comparator circuit configured to compare a first input signal to a second input signal. The comparator circuit includes at least one regenerative latch circuit having a first and second inputs configured to receive the first and second input signals, respectively. The comparator circuit further includes a clock circuit configured to generate and provide a clock signal exclusively to circuitry in the comparator circuit, including the at least one regenerative latch circuit. At least one output latch circuit coupled to the at least one regenerative latch circuit and configured to provide a first output signal indicative of a comparison of the first and second input signals.

An ANC system is provided, including an AD converter performing an AD conversion on an external noise signal; an ANC signal generator generating an ANC signal for canceling a noise component arriving at ears of a user based on an output signal of the AD converter; a level detector detecting a level of the output signal and causes the ANC signal generator to power down in response to the level; and a zero-cross detector detecting a zero-cross timing of the ANC signal. The level detector starts measuring a time when the level is equal to or less than a first threshold value, and causes the ANC signal generator to perform a power down operation when the zero-cross timing is detected after the measured time exceeds the predetermined value, and causes the ANC signal generator to exit from the power down operation when the level exceeds a second threshold value.

An ANC system is provided, including an AD converter performing an AD conversion on an external noise signal; an ANC signal generator generating an ANC signal for canceling a noise component arriving at ears of a user based on an output signal of the AD converter; a level detector detecting a level of the output signal and causes the ANC signal generator to power down in response to the level; and a zero-cross detector detecting a zero-cross timing of the ANC signal. The level detector starts measuring a time when the level is equal to or less than a first threshold value, and causes the ANC signal generator to perform a power down operation when the zero-cross timing is detected after the measured time exceeds the predetermined value, and causes the ANC signal generator to exit from the power down operation when the level exceeds a second threshold value.

A circuit arrangement for monitoring an alternating voltage signal includes a comparator configured to receive the alternating voltage signal or a signal obtained from the alternating voltage signal at a first comparator input and output a comparator signal at a comparator output. The circuit arrangement further includes a zero crossing detector configured to receive a reference signal or a signal obtained from the reference signal at a monitoring input and generate a detector signal at an output of the zero crossing detector. The circuit arrangement further includes a logic circuit including a first timing element connected downstream of the zero crossing detector for generating a first clock signal and a second timing element connected downstream of the zero crossing detector for generating a second clock signal.

A circuit arrangement for monitoring an alternating voltage signal includes a comparator configured to receive the alternating voltage signal or a signal obtained from the alternating voltage signal at a first comparator input and output a comparator signal at a comparator output. The circuit arrangement further includes a zero crossing detector configured to receive a reference signal or a signal obtained from the reference signal at a monitoring input and generate a detector signal at an output of the zero crossing detector. The circuit arrangement further includes a logic circuit including a first timing element connected downstream of the zero crossing detector for generating a first clock signal and a second timing element connected downstream of the zero crossing detector for generating a second clock signal.

The present disclosure discloses a zero-crossing detection circuit, including: a zero-crossing judgment module, having a first end and a second end, wherein the first end is connected to a power supply and the second end is grounded; a photoelectric coupler, connected to the zero-crossing judgment module; an optocoupler driving module, connected to the photoelectric coupler; and an energy storage capacitor, wherein the energy storage capacitor is configured to provide excitation power for the photoelectric coupler and the optocoupler driving module.

The present disclosure discloses a zero-crossing detection circuit, including: a zero-crossing judgment module, having a first end and a second end, wherein the first end is connected to a power supply and the second end is grounded; a photoelectric coupler, connected to the zero-crossing judgment module; an optocoupler driving module, connected to the photoelectric coupler; and an energy storage capacitor, wherein the energy storage capacitor is configured to provide excitation power for the photoelectric coupler and the optocoupler driving module.

A drive circuit with a zero-crossing detection function, and a zero-crossing detection method. The drive circuit comprises: a power switch transistor, a pull-up drive transistor, a first pull-down drive transistor and a second pull-down drive transistor. When an inductor starts to discharge, the first pull-down current and the second pull-down current jointly pull down a gate terminal of the power switch transistor, such that the power switch transistor is in a cut-off state; after a set time, the first pull-down current is turned off; and when the inductor ends discharging, a parasitic capacitance of the power switch transistor couples with the drop signal, and when the drop signal is detected, the pull-up current pulls up the gate terminal of the power switch transistor, such that the power switch transistor is in a turn-on state.

A drive circuit with a zero-crossing detection function, and a zero-crossing detection method. The drive circuit comprises: a power switch transistor, a pull-up drive transistor, a first pull-down drive transistor and a second pull-down drive transistor. When an inductor starts to discharge, the first pull-down current and the second pull-down current jointly pull down a gate terminal of the power switch transistor, such that the power switch transistor is in a cut-off state; after a set time, the first pull-down current is turned off; and when the inductor ends discharging, a parasitic capacitance of the power switch transistor couples with the drop signal, and when the drop signal is detected, the pull-up current pulls up the gate terminal of the power switch transistor, such that the power switch transistor is in a turn-on state.

An apparatus may include global control module, the global control module including a digital master clock generator and a master waveform generator. The apparatus may also include a plurality of resonator control modules, coupled to the global control module. A given resonator control module of the plurality of resonator control modules may include a synchronization module, having a first input coupled to receive a resonator output voltage pickup signal from a local resonator, a second input coupled to receive a digital master clock signal from the digital master clock generator, and a first output coupled to send a delay signal to the master waveform generator.