A duty margin monitoring circuit, coupled to a functional circuit which generates a first output signal in response to a target signal, includes a modulation circuit, a replica circuit and an error detection circuit. The modulation circuit is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. The replica circuit is arranged to receive the modulated target signal and generate a second output signal in response to the modulated target signal. The error detection circuit is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and arranged to generate an error detection result according to the first output signal and the second output signal.

One embodiment of a duty-cycle corrector phase shift (DCCPS) circuit includes a voltage-controlled delay line circuit, a duty-cycle correct circuit, an error amplifier circuit, and DC sampler circuits. Another embodiment of a duty-cycle corrector phase shift circuit includes a digital-controlled delay line circuit, a duty-cycle correct circuit, DC sampler circuits, a comparator circuit, a counter circuit, a control circuit, and a lock detector circuit. In some instances, the DCCPS circuit provides a clock signal with a duty-cycle of approximately fifty percent (50%) and a given phase shift between an input clock signal and the output clock signal.

Systems and methods for adaptively adjusting a slew rate of a dejitter buffer in a remote device in a distributed access architecture. The slew rate may be adjusted based on measurements of a fullness state of a buffer made over time. The measurements may be used to calculate a frequency offset value between the rate at which data leaves the buffer relative to the rate at which data enters the buffer and/or used to calculate a current working depth of the buffer. The adaptive slew rate adjustments may be based on the frequency offset value and/or the current working depth.

A system for driving a transducer having a plurality of coils, the system comprising: a modulator for outputting a digital output signal representative of a received analogue input signal at a modulator output; a clock controlled delay element for applying a delay to the digital output signal to generate a first delayed signal at a delay element output; wherein the modulator output is couplable to a first coil of the plurality of the coils of the transducer and the delay element output is couplable to a second coil of the plurality of coils of the transducer.

A duty timing detector includes: a control logic, the control logic being configured to: receive an input toggle signal and an output toggle signal that corresponds to the input toggle signal, and generate a difference signal using a difference between a duty of the input toggle signal and a duty of the output toggle signal; a first low-pass filter configured to output a DC input voltage based on a pulse width of the input toggle signal; a second low-pass filter configured to output a DC difference voltage based on a pulse width of the difference signal; a compensation circuit configured to compensate the duty of the output toggle signal using the DC input voltage and the DC difference voltage; and an oscillator configured to generate a duty-compensated output toggle signal, and to provide the duty-compensated output toggle signal to the control logic.

A duty cycle correction circuit includes a sawtooth wave generating unit, a voltage regulating unit, a differential comparator, a differential amplifier and low-pass filters. The sawtooth wave generating unit converts a narrow pulse signal into a sawtooth wave signal with a duty cycle of 50% which is input into the differential comparator. The voltage regulating unit regulates an input voltage value of a non-inverting input terminal of the differential comparator. The differential comparator compares a voltage difference between input signals of input terminals and outputs an output clock signal. The low-pass filters input DC components to the differential amplifier which amplifies the DC signals and output to the voltage regulating unit. The duty cycle correction circuit has a small chip occupying area to realize high integration of the chip, and the duty cycle of the output clock is accurately corrected to ensure the stability of the output clock frequency.

An example of an apparatus may include NAND memory and circuitry coupled to the NAND memory to provide duty cycle correction (DCC) for one or more write paths of the NAND memory. Other examples are disclosed and claimed.

A method includes performing a duty-cycle correction. The method can include inputting a signal to a duty-cycle correction circuit. The method can further include transferring the signal through an alternating current-coupling (AC-coupling) component of the duty-cycle correction circuit. The method can further include transferring the signal through a feedback circuit, wherein the feedback circuit comprises a plurality of resistors. The method can further include outputting a signal that includes a corrected duty-cycle with a particular amount of duty-cycle distortion.

A clock synthesizer is provided. The Clock synthesizer includes a Phase Locked Loop (PLL) configured to generate a clock signal based on a reference signal. A clock buffer is connected to the PLL. The clock buffer stores the clock signal. A Duty Cycle Controller and Phase Interpolator (DCCPI) circuit is connected to the clock buffer. The DCCPI circuit receives the clock signal from the clock buffer, adjusts a duty cycle of the clock signal to substantially equal to 50%, performs phase interpolation on the clock signal, and provides the clock signal as an output after adjusting the duty cycle substantially equal to 50% and performing the phase interpolation.

A clock circuit includes a set of level shifters, a duty cycle adjustment circuit and a calibration circuit. The set of level shifters is configured to output a first set of phase clock signals having a first duty cycle. Each level shifter is configured to output a corresponding phase clock signal of the first set of phase clock signals. The duty cycle adjustment circuit is configured to generate a first clock output signal responsive to at least one of a first or second phase clock signal of the first set of phase clock signals or a set of control signals. The first clock output signal has a second duty cycle. The calibration circuit is configured to perform a duty cycle calibration of the second duty cycle based on an input duty cycle, and generate the set of control signals responsive to the duty cycle calibration of the second duty cycle.