A decision feedback equalizer includes a comparator configured to output a constant voltage in a reset period and to output a differential voltage corresponding to differential input signals in an evaluation period, a latch circuit configured to hold the differential voltage in the evaluation period, and an adjuster configured to adjust a logical threshold of the latch circuit closer to the output voltage in the reset period.

An injection-locked oscillator includes an oscillator and an injection circuit. The oscillator includes a first oscillation node through which a first oscillation signal is output and a second oscillation node through which a second oscillation signal is output, the second oscillation signal having a phase opposite to that of the first oscillation signal. The injection circuit provides an injection current between the first oscillation node and the second oscillation node according to a reference signal. The injection circuit includes a charging element configured to be charged or discharged in response to a reference signal and to provide the injection current between the first oscillation node and the second oscillation node.

In an embodiment, an apparatus is disclosed that includes a duty cycle controller. The duty cycle controller includes a tuning circuit comprising a first field-effect transistor. The first field-effect transistor is configured to implement a capacitor. The duty cycle controller further includes an edge delay circuit. The edge delay circuit includes a second field-effect transistor that, when activated by an input clock signal of the duty cycle controller, is configured to connect a voltage source to an output clock signal of the duty cycle controller. The edge delay circuit further includes a third field-effect transistor that, when activated, is configured to connect the first field-effect transistor of the tuning circuit to the output clock signal.

A clock generation circuit coupled to an integrator circuit uses a variable resistance that is adjusted in a transconductance bias feedback circuit. This resistance is calibrated to the reciprocal of the transconductance of the input amplifier. The product of the adjusted resistance and a capacitance in the clock generation circuit provides a time constant for the settling time of the integrator and controls a pulse width of an adaptively controlled duty cycle output clock.

Various methods and devices that involve pulsed signals are disclosed. An example minimum pulse-width (MPW) circuit comprises a first and second logic circuit. A first input of the first logic circuit is connected to an input of the MPW circuit. A first input of the second logic circuit is communicatively coupled to an output of the first logic circuit. The MPW circuit also comprises a MPW filter circuit communicatively coupled to an output of the second logic circuit, a one-shot circuit communicatively coupled to an output of the minimum pulse-width filter circuit and located on a first feedback path, and another one-shot circuit communicatively coupled to the output of the minimum pulse-width filter circuit and located on a second feedback path. A second input of the first logic circuit is on the first feedback path. A second input of the second logic circuit is on the second feedback path.

An electrical circuit device includes a signal bus comprising a plurality of parallel signal paths and a calibration circuit, operatively coupled with the signal bus. The calibration circuit can perform operations including determining a representative duty cycle for a plurality of signals transferred via the plurality of parallel signal paths, the plurality of signals comprising a plurality of duty cycles and comparing the representative duty cycle for the plurality of signals transferred via the plurality of parallel signal paths to a reference value to determine a comparison result. The calibration circuit can perform further operations including adjusting, based on the comparison result, a trim value associated with the plurality of duty cycles of the plurality of signals to compensate for distortion in the plurality of duty cycles and calibrating the plurality of duty cycles of the plurality of signals using the adjusted trim value.

A device for generating a duty cycle includes a converter, a corrector, and a control circuit. The converter is configured to generate a first output signal having a duty cycle to an output terminal according to an input signal. The corrector is coupled to the output terminal, and is configured to adjust the duty cycle of the first output signal according to a control signal. The converter is coupled in parallel with the corrector and between a first power source and a second power source. The control circuit is coupled to the output terminal, and is configured to generate the control signal according to the first output signal and a reference signal.

A duty cycle correction circuit includes a first duty cycle detecting circuit configured to detect a duty cycle of a clock signal with a first resolution; a reference clock generating circuit configured to generate a reference clock signal by adjusting a phase of the clock signal; a second duty cycle detecting circuit configured to detect a duty cycle of the clock signal with a second resolution according to the reference clock signal and the clock signal, the second resolution being finer than the first resolution; a first duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more first control signals output from the first duty cycle detecting circuit; and a second duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more second control signals output from the second duty cycle detecting circuit.

A duty cycle correction circuit includes a detection block suitable for detecting a duty cycle of a first clock in response to the first clock and a second clock, and a correction block suitable for generating a first corrected clock having a corrected duty cycle relative to the first clock and a second corrected clock having a corrected duty cycle relative to the second clock, based on a detection result of the detection block.

A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.