Embodiments include systems and methods for detecting and correcting phased clock error (PCE) in phased clock circuits (e.g., in context of serializer/deserializer (SERDES) transmission (TX) clock circuits). For example, phased input clock signals can be converted into unit interval (UI) clocks, which can be combined to form an output clock signal. PCE in the output clock signal can be detected by digitally sampling the UI clocks to characterize their respective clock pulse widths, and comparing the respective clock pulse widths (i.e., PCE in the output clock signal can result from pulse width differences in UI clocks). Delay can be applied to one or more UI clock generation paths to shift UI clock pulse transitions, thereby adjusting output clock pulse widths to correct for the detected PCE. Approaches described herein can achieve PCE detection over a wide error range and can achieve error correction with small resolution.

At least one method, apparatus and system disclosed involves performing a dynamic voltage compensation in an integrated circuit. A first voltage on a first portion of an integrated circuit is received. A second voltage on a second portion of the integrated circuit is monitored. A determination is made as to whether the second voltage fell below the first voltage by a predetermined margin. A feedback adjustment of the of the second voltage is performed in response to a determination that the second voltage fell below the first voltage by the predetermined margin; the feedback adjustment comprises performing a step up of the second voltage.

In described examples, a pulse width modulation (PWM) system includes an initiator and a receiver. The initiator includes an initiator counter and an initiator PWM signal generator. The initiator counter advances an initiator count in response to an initiator clock signal. The initiator PWM signal generator generates an initiator PWM signal in response to the initiator count. The receiver includes a receiver counter, a receiver PWM signal generator, and circuitry configured to reset the receiver count. The receiver counter advances a receiver count in response to a receiver clock signal. The receiver PWM signal generator generates a receiver PWM signal in response to the receiver count. The circuitry resets the receiver count in response to a synchronization signal and based on an offset.

A clock correction device performs skew adjustment and duty correction of an input clock concurrently or in parallel. The clock correction device includes a correction circuit that performs skew adjustment of an input clock by analog control using a skew adjustment signal based on a phase difference between an output clock and a reference clock, receives a duty control signal, and performs duty correction of the input clock by digital control, a skew detection circuit that receives inputs of the output clock and the reference clock and, when only the reference clock is in a predetermined state, outputs a detection signal that changes to the predetermined state, an integration circuit that integrates the detection signal and generates a first voltage signal, and a comparator that compares the first voltage signal and a first reference signal to thereby generate the skew adjustment signal.

A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.

A frequency divider circuit includes: a first frequency dividing circuit configured to divide a first clock signal to generate a first frequency-divided clock signal; a second frequency dividing circuit configured to divide a second clock signal having the same frequency as the first clock signal and having a first phase difference with respect to the first clock signal to generate a second frequency-divided clock signal; a detection circuit configured to detect a phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal; and a selection circuit configured to select and output one of the second frequency-divided clock signal and an inverted signal of the second frequency-divided clock signal which are generated by the second frequency dividing circuit, based on the phase relationship between the first frequency-divided clock signal and the second frequency-divided clock signal detected by the detection circuit.

A method of measuring duty-cycle distortion in a signal (e.g., flowing between an operating circuit and a memory circuit), where the signal has a known period, the signal being measured is in a first state during a first portion of the period, and is in a different state during a second portion of the period, includes advancing or retarding the signal until an edge of the signal intersects an edge of the other signal. From the amount of the advancing or retarding, the duty cycle and the magnitude of duty-cycle distortion are determined. This may be used to control correction of the duty-cycle distortion. An interpolator circuit may be used to advance or retard the signal. A processor may be used to keep track of the amount of advancing or retarding, to determine the duration of the duty cycle, and control correction of the duty-cycle distortion.

Methods, systems, and devices for phase clock correction are described. The clock correction may, in some examples, include two stages of duty cycle adjustment. In a first stage, the duty cycles of multiple clock signals may be adjusted. These clock signals may be based on an input clock signal and its complement. The duty cycle adjustment provided to a clock signal during this stage may be based on a difference between the duty cycle of the clock signal before adjustment and the duty cycle of another clock signal. In the second stage, the duty cycle of the input clock signal and its complement may be adjusted. The duty cycle adjustment provided to the input clock signal and/or its complement may be based on clock signals generated from the multiple clock signals after their duty cycles have been adjusted.

A clock generation circuit includes a control clock generation circuit and first and second clock synchronization circuits. The control clock generation circuit compares a reference voltage with first and second feedback clock signals to generate first and second control clock signals. The first clock synchronization circuit makes the first and second feedback clock signals transit in synchronization with the first and second control clock signals. The second clock synchronization circuit generates first and second phase clock signals in synchronization with the first feedback clock signal and the second feedback clock signal.

The present technology relates to a signal processing apparatus and a signal processing method that allow easy adjustment of a pulse duty ratio.

A phase comparison section outputs a phase difference signal corresponding to a phase difference between rising edges or falling edges of a first pulse and a second pulse. The first pulse is used as a basis at the time of adjusting a duty ratio, and the second pulse has a duty ratio that is to be adjusted. A reference signal generation section outputs a reference signal that starts changing according to the first pulse. A comparison section outputs a comparison output signal representing a magnitude relation between the phase difference signal and the reference signal, and the comparison output signal is fed back as the second pulse. The present technology is applicable to a case of adjusting a duty ratio of a pulse.