The present invention provides a pressure detection circuit including an oscillator unit, configured to output an oscillation signal as a count clock signal of a counter unit; and the counter unit, connected to the oscillator unit and configured to acquire a frequency of the oscillation signal and count. The pressure detection circuit further includes a comparator unit, connected to the counter unit, and configured to detect a voltage variation obtained by a pressure conversion, and send a signal to control the counter unit to count or stop counting; a voltage converter unit, connected to one input terminal of the comparator unit, and configured to supply a fixed or variable comparable voltage to the comparator unit; a constant current source charging unit, connected to the other input terminal of the comparator unit, and configured to supply a linearly and gradually increased comparison voltage to the comparator unit; a charge/discharge control unit, connected to the constant current source charging unit, and configured to control the constant current source charging unit to charge or discharge, such that the comparable voltage output by the voltage converter unit is compared to cause an output terminal of the comparator unit to enable counting of the counter unit; wherein the oscillator unit or the voltage converter unit further includes a pressure acquiring unit, as a component of the voltage converter unit or the oscillator unit, configured to convert a pressure into a variation of the comparable voltage or the frequency of the oscillation signal. The invention also provides a pressure input device pressure detection device. The invention has the technical effects of high sensitivity and resolution, power saving, and wide applicability.

The present invention provides a pressure detection circuit including an oscillator unit, configured to output an oscillation signal as a count clock signal of a counter unit; and the counter unit, connected to the oscillator unit and configured to acquire a frequency of the oscillation signal and count. The pressure detection circuit further includes a comparator unit, connected to the counter unit, and configured to detect a voltage variation obtained by a pressure conversion, and send a signal to control the counter unit to count or stop counting; a voltage converter unit, connected to one input terminal of the comparator unit, and configured to supply a fixed or variable comparable voltage to the comparator unit; a constant current source charging unit, connected to the other input terminal of the comparator unit, and configured to supply a linearly and gradually increased comparison voltage to the comparator unit; a charge/discharge control unit, connected to the constant current source charging unit, and configured to control the constant current source charging unit to charge or discharge, such that the comparable voltage output by the voltage converter unit is compared to cause an output terminal of the comparator unit to enable counting of the counter unit; wherein the oscillator unit or the voltage converter unit further includes a pressure acquiring unit, as a component of the voltage converter unit or the oscillator unit, configured to convert a pressure into a variation of the comparable voltage or the frequency of the oscillation signal. The invention also provides a pressure input device pressure detection device. The invention has the technical effects of high sensitivity and resolution, power saving, and wide applicability.

Embodiments of a power converter are disclosed. In an embodiment, the power converter comprises a power factor correction (PFC) stage circuit, an emulation circuit and a controller. The PFC stage circuit is configured to produce an output signal on an output terminal. The PFC stage circuit includes an inductor coupled between a rectifier and the output terminal and a switch coupled to the inductor. The emulation circuit is connected to the PFC stage circuit to generate an emulated current that corresponds to current through the inductor of the PFC stage circuit. The emulated current is generated based on a voltage signal at a node between the inductor and the output terminal and a sensed current at a sense resistor connected to the rectifier. The controller is connected to the emulation circuit to receive the emulated current and generate a control signal for the switch of the PFC stage circuit based on the emulated current.

Embodiments of a power converter are disclosed. In an embodiment, the power converter comprises a power factor correction (PFC) stage circuit, an emulation circuit and a controller. The PFC stage circuit is configured to produce an output signal on an output terminal. The PFC stage circuit includes an inductor coupled between a rectifier and the output terminal and a switch coupled to the inductor. The emulation circuit is connected to the PFC stage circuit to generate an emulated current that corresponds to current through the inductor of the PFC stage circuit. The emulated current is generated based on a voltage signal at a node between the inductor and the output terminal and a sensed current at a sense resistor connected to the rectifier. The controller is connected to the emulation circuit to receive the emulated current and generate a control signal for the switch of the PFC stage circuit based on the emulated current.

Receiver circuitry for a communication system includes signal processing circuitry, voltage digital-to-analog converter (DAC) circuitry, and slicer circuitry. The signal processing circuitry receives a data signal and generate a processed data signal. The voltage DAC circuitry generates a first threshold reference voltage. The slicer circuitry is coupled to an output of the signal processing circuitry. The slicer circuitry includes a capture flip-flop (CapFF) circuit that receives the processed data signal and the first threshold reference voltage. The CapFF circuit further generates a first data signal. The first CapFF circuit includes a first offset compensation circuit that adjusts a parasitic capacitance of the first CapFF circuit.

An electronic device has a first circuit, a second circuit, and an isolation circuit, the isolation circuit having an input and an output, the first circuit including a signal generator having an output, the output of the signal generator coupled to the input of the isolation circuit. The second circuit includes a rectifier circuit and a signal detector circuit, the rectifier circuit having a rectifier input coupled to the output of the isolation circuit, and the signal detector circuit having an input coupled to the output of the isolation circuit.

An electronic device has a first circuit, a second circuit, and an isolation circuit, the isolation circuit having an input and an output, the first circuit including a signal generator having an output, the output of the signal generator coupled to the input of the isolation circuit. The second circuit includes a rectifier circuit and a signal detector circuit, the rectifier circuit having a rectifier input coupled to the output of the isolation circuit, and the signal detector circuit having an input coupled to the output of the isolation circuit.

A direct current (DC) to DC (DC-DC) converter includes a comparator setting a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL adjusting the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer selectively outputting a delayed version of the signal pulse; a phase detector operatively coupled to a system clock and the multiplexer, the phase detector generating a phase error between an output of the multiplexer and the system clock; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit adjusting the delay introduced to the signal pulse in accordance with the phase error.

A direct current (DC) to DC (DC-DC) converter includes a comparator setting a pulse width of a signal pulse, the pulse width corresponding to a voltage level of an output voltage of the DC-DC converter; a digital delay line (DDL) operatively coupled to the comparator, the DDL adjusting the pulse width of the signal pulse by linearly introducing delays to the signal pulse; a multiplexer operatively coupled to the DDL, the multiplexer selectively outputting a delayed version of the signal pulse; a phase detector operatively coupled to a system clock and the multiplexer, the phase detector generating a phase error between an output of the multiplexer and the system clock; and a logic control circuit operatively coupled to the multiplexer and the DDL, the logic control circuit adjusting the delay introduced to the signal pulse in accordance with the phase error.

There is provide a current detection circuit including: a current detection unit that detects a control current flowing between a control terminal of a semiconductor element of voltage-controlled type having a current detection terminal, and a drive circuit; an overcurrent detection unit that detects an overcurrent in response to a sense current exceeding an overcurrent threshold value, the sense current flowing through the current detection terminal; and an adjustment unit that sets, based on a detection result of the current detection unit, the overcurrent threshold value in a transient period during turn on and turn off of the semiconductor element to be higher than the overcurrent threshold value in a period other than the transient period.