An envelope detector comprises a first differential transistor pair that receives first and second input signals, a second differential transistor pair that receives third and fourth input signals, a resistor, a current source, and a comparator. The first and second differential pairs each comprise two transistors having first current terminals coupled together and second current terminals coupled together. The resistor is coupled between the second current terminals of the first and second differential pairs. The current source has a first terminal coupled to the second terminal of the resistor and to second current terminals of the second differential pair and a second terminal configured to receive a negative supply voltage. The comparator has a negative input coupled to first current terminals of the first differential pair and a positive input coupled to first current terminals of the second differential pair.

Example implementations include a method of obtaining an input voltage of a power converter circuit and a system voltage of the power converter circuit, obtaining a voltage rate gain based on an aggregate inductance of the power converter circuit, and in accordance with a determination that the input voltage and the system voltage are not equal, generating a rate offset voltage based on the voltage rate gain and the system voltage difference. Example implementations also include a device with a rate predictor device operatively coupled to an input voltage node and a system voltage node, and configured to obtain an input voltage of a power converter circuit and a system voltage of the power converter circuit, configured to obtain a voltage rate gain based on an aggregate inductance of the power converter circuit, and configured to, in accordance with a determination that the input voltage and the system voltage are not equal, generate a rate offset voltage based on the voltage rate gain and the system voltage difference.

Example implementations include a method of obtaining an input voltage of a power converter circuit and a system voltage of the power converter circuit, obtaining a voltage rate gain based on an aggregate inductance of the power converter circuit, and in accordance with a determination that the input voltage and the system voltage are not equal, generating a rate offset voltage based on the voltage rate gain and the system voltage difference. Example implementations also include a device with a rate predictor device operatively coupled to an input voltage node and a system voltage node, and configured to obtain an input voltage of a power converter circuit and a system voltage of the power converter circuit, configured to obtain a voltage rate gain based on an aggregate inductance of the power converter circuit, and configured to, in accordance with a determination that the input voltage and the system voltage are not equal, generate a rate offset voltage based on the voltage rate gain and the system voltage difference.

An apparatus includes a resistor having a resistor terminal. The apparatus includes a capacitor coupled to the resistor terminal. The apparatus includes a transistor having a current terminal and a gate. The gate is coupled to the resistor terminal and coupled to the capacitor. The apparatus includes a comparator having a comparator input and a comparator output. The comparator input is coupled to the current terminal. The apparatus includes a latch having a latch input coupled to the comparator output.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

An integrated circuit includes a first circuit block operating with a first clock signal and a second circuit block operating with a second clock signal. The first circuit block includes a clock phase generator that receives the first clock signal and outputs a plurality of phase signals. The first circuit block includes a phase selector that receives the phase signals and the second clock signal and selects one of the phase signals based on the second clock signal. The first circuit block transmits data to the second circuit block based on the selected phase signal.

An integrated circuit includes a first circuit block operating with a first clock signal and a second circuit block operating with a second clock signal. The first circuit block includes a clock phase generator that receives the first clock signal and outputs a plurality of phase signals. The first circuit block includes a phase selector that receives the phase signals and the second clock signal and selects one of the phase signals based on the second clock signal. The first circuit block transmits data to the second circuit block based on the selected phase signal.

The present disclosure provides a data mutex filter circuit and a data mutex filtering method. The data mutex filter circuit has a main input terminal and a main output terminal and including a preprocessing sub-circuit and a 1st-stage filter sub-circuit to an Nth-stage filter sub-circuit which are cascaded, N being an integer greater than or equal to 2. The 1st-stage filter sub-circuit has an input terminal coupled to the preprocessing sub-circuit, and the Nth-stage filter sub-circuit has an output terminal coupled to the main output terminal. Each stage of filter sub-circuit is configured to compare whether input data currently received at the main input terminal is the same as history data stored therein, and feed back a comparison result to the preprocessing sub-circuit; the preprocessing sub-circuit outputs corresponding data to the 1st-stage filter sub-circuit according to the comparison result fed back by each stage of filter sub-circuit.

The present disclosure provides a data mutex filter circuit and a data mutex filtering method. The data mutex filter circuit has a main input terminal and a main output terminal and including a preprocessing sub-circuit and a 1st-stage filter sub-circuit to an Nth-stage filter sub-circuit which are cascaded, N being an integer greater than or equal to 2. The 1st-stage filter sub-circuit has an input terminal coupled to the preprocessing sub-circuit, and the Nth-stage filter sub-circuit has an output terminal coupled to the main output terminal. Each stage of filter sub-circuit is configured to compare whether input data currently received at the main input terminal is the same as history data stored therein, and feed back a comparison result to the preprocessing sub-circuit; the preprocessing sub-circuit outputs corresponding data to the 1st-stage filter sub-circuit according to the comparison result fed back by each stage of filter sub-circuit.