Circuits and methods for transmitting high-voltage (HV) static and/or switching signals via a high-voltage (HV) transmission gate controllable via low-voltage (LV) logic are presented. The HV gate includes a biasing circuit for generating a biasing voltage to gates of two series-connected HV transistors. According to one aspect, the biasing voltage is generated through a pull-up device coupled to a HV supply having a voltage level higher than a high voltage of a signal to be transmitted. According to another aspect, the biasing voltage is generated through a LV supply coupled to a diode, and a capacitor coupled between the gates and the sources of the HV transistors. When the gate is activated, the combination of the LV supply coupled to the diode and the capacitor generates a biasing voltage based on a sum of a voltage of the LV supply and an instantaneous voltage level of the signal being transmitted.

A transistor diagnostic circuit includes a protection transistor output terminal, a fault terminal, and circuitry coupled to the protection transistor output terminal and the fault terminal. The protection transistor output terminal is adapted to be coupled to a current terminal of a protection transistor. The transistor diagnostic circuit is configured to, at start-up, load the protection transistor output terminal to test the protection transistor, and to generate a fault signal at the fault terminal responsive to a voltage on the protection transistor output terminal exceeding a threshold.

A switch device is provided. The switch device includes a switch and a one-way link circuit, wherein the switch including a first port, a second port, and a third port. The third port coupled to the second port via a first path and coupled to the first port via a second path. An input terminal of the one-way link circuit is coupled to the first port.

An integrated circuit includes an input terminal, an input buffer circuit, an interface voltage control circuit, an output voltage selection circuit, an output driver circuit, and an output terminal. The input buffer circuit is coupled to the input terminal. The interface voltage control circuit is coupled to the input terminal. The output voltage selection circuit is coupled to the interface voltage control circuit. The output driver circuit is coupled to the output voltage selection circuit. The output terminal is coupled to the output driver circuit.

A nanosecond pulser is disclosed. In some embodiments, the nanosecond pulser may include one or more switch circuits including one or more solid state switches, a transformer, and an output. In some embodiments, the transformer may include a first transformer core, a first primary winding wound at least partially around a portion of the first transformer core, and a secondary winding wound at least partially around a portion of the first transformer core. In some embodiments, each of the one or more switch circuits are coupled with at least a portion of the first primary winding. In some embodiments, the output may be electrically coupled with the secondary winding and outputs electrical pulses having a peak voltage greater than about 1 kilovolt and a rise time of less than 150 nanoseconds or less than 50 nanoseconds.

An electronic device includes a multiplexer (MUX), a switching array and logic circuitry. The MUX includes multiple input ports and an output port, and is configured to receive, via the input ports, multiple input signals, and to output, via the output port, a selected signal among the input signals. The switching array is coupled to the input ports of the MUX and is configured to receive the input signals and to connect or disconnect between each input signal and a respective input port. The logic circuitry is electrically coupled to the switching array and to the MUX, and is configured to control the switching array to connect at least the selected signal that the MUX is outputting, and to disconnect all the input signals other than the at least selected signal.

A multiplexer device includes a plurality of selection circuits and potential setting circuits. The plurality of selection circuits respectively receive a first data signal and a second data signal, and select a corresponding one of the first data signal and the second data signal as an output signal according to the first selection signal. When the second data signal is selected as the output signal, the potential setting circuit sets a potential of a node of a first selection circuit of the plurality of selection circuits to a first voltage. The first selection circuit is configured to receive a first data signal.

A power source selection system can include a primary source line configured to be connected to a primary source having a primary voltage, a backup source line configured to connect to a backup source having a backup voltage, and a voltage divider and limiter connected to the primary source line to receive the primary voltage and to provide an sense signal on a sense line. The system can include a NAND gate connected to the voltage divider and limtier to receive the sense signal. The NAND gate can be configured to provide a gate signal to a gate line based on the sense signal. The system can include a switchover circuit connected to the backup source line and the gate line to receive the backup voltage and the gate signal. The switchover circuit can be configured to output the backup voltage to a switch line in a first state, and to prevent backup voltage to the switch line in a second state. The switchover circuit can be configured to switch between the first state and the second state based on the gate signal. The system can include an ORing circuit connected to the primary source line and to the switch line. The ORing circuit can be configured to select between the primary voltage and backup voltage and to output the selected voltage as the output voltage.

A superconducting DC switch system is provided. The superconducting DC switch system comprises one or more Josephson junctions (JJs), and a magnetic field generator that is configured to switch from inducing a magnetic field in a plane of the one or more JJs, and providing no magnetic field in the plane of the one or more JJs. A DC input signal applied at an input of the one or more JJs is passed through to an output the one or more JJs in the absence of an induced magnetic field, and the DC input signal is substantially suppressed at the output of the one or more JJs in the presence of the magnetic field.

Circuits and methods for transmitting high-voltage (HV) static and/or switching signals via a high-voltage (HV) transmission gate controllable via low-voltage (LV) logic are presented. The HV gate includes a biasing circuit for generating a biasing voltage to gates of two series-connected HV transistors. According to one aspect, the biasing voltage is generated through a pull-up device coupled to a HV supply having a voltage level higher than a high voltage of a signal to be transmitted. According to another aspect, the biasing voltage is generated through a LV supply coupled to a diode, and a capacitor coupled between the gates and the sources of the HV transistors. When the gate is activated, the combination of the LV supply coupled to the diode and the capacitor generates a biasing voltage based on a sum of a voltage of the LV supply and an instantaneous voltage level of the signal being transmitted.