Some embodiments may include a nanosecond pulser comprising a plurality of solid state switches; a transformer having a stray inductance, L.sub.s, a stray capacitance, C.sub.s, and a turn ratio n; and a resistor with a resistance, R, in series between the transformer and the switches. In some embodiments, the resonant circuit produces a Q factor according to

[00001]$Q=\frac{1}{R}.Math.\sqrt{\frac{L_s}{C_s}};$

and the nanosecond pulser produces an output voltage V.sub.out from an input voltage V.sub.in, according to V.sub.out=QnV.sub.in.

A nanosecond pulser is disclosed. In some embodiments, the nanosecond pulser may include one or more switch circuits including one or more solid state switches, a transformer, and an output. In some embodiments, the transformer may include a first transformer core, a first primary winding wound at least partially around a portion of the first transformer core, and a secondary winding wound at least partially around a portion of the first transformer core. In some embodiments, each of the one or more switch circuits are coupled with at least a portion of the first primary winding. In some embodiments, the output may be electrically coupled with the secondary winding and outputs electrical pulses having a peak voltage greater than about 1 kilovolt and a rise time of less than 150 nanoseconds or less than 50 nanoseconds.

The present invention provides a circuit for controlling a voltage for driving liquid lens including a first voltage generator for outputting a first voltage; a second voltage generator for outputting a second voltage having an opposite polarity to the first voltage; a first switch for selecting one of the first voltage and a ground voltage, and transmitting the selected voltage; a second switch for selecting one of the second voltage and the ground voltage, and transmitting the selected voltage; and a third switch for selecting one of a voltage selected by the first switch and the voltage selected by the second switch, and transmitting the selected voltage, wherein the third switches is plural in number, and the first switch is connected in common to the plurality of third switches.

An NMOS switch driving circuit and a power supply device are provided. The NMOS switch driving circuit includes a power-supply unit, a switch unit, a power conversion unit, and a driving unit. The power-supply unit is configured to output a first voltage. The switch unit is electrically coupled between the power-supply unit and a first interface and configured to establish or disconnect an electrical coupling between the power-supply unit and the first interface. The power conversion unit includes a port coupled to the power-supply unit and another port electrically coupled to the switch unit via the driving unit. The power conversion unit is configured to convert the first voltage into a constant driving voltage and output the driving voltage to the switch unit via the driving unit to drive the switch unit to be switched on, to establish the electrical coupling between the power-supply unit and the first interface.

A multiplexer device includes a plurality of selection circuits and potential setting circuits. The plurality of selection circuits respectively receive a first data signal and a second data signal, and select a corresponding one of the first data signal and the second data signal as an output signal according to the first selection signal. When the second data signal is selected as the output signal, the potential setting circuit sets a potential of a node of a first selection circuit of the plurality of selection circuits to a first voltage. The first selection circuit is configured to receive a first data signal.

A pre-charge circuit is provided for pre-charging the input node of a capacitive component to which the multiplexer output is fed to a charge level that is close to or approximates the signal output level of the multiplexer when its output is next switched. In order to reduce the level shifting burden on the amplifier in the pre-charge circuit, each pre-charge circuit input channel has a respective capacitor that is able to be switched in and out of series with the respective multiplexer channels, such that the respective capacitors track the signal levels on the multiplexer channels. The provision of the corresponding capacitors for each MUX channel reduces the input current to the pre-charge amplifier, and allows for the level shifting burden to be taken by the capacitors, leading to more stable and lower power operation.

A power transmission circuit includes a first transmission transistor, a second transmission transistor, and a first control circuit. A first terminal of the first transmission transistor is used as a power input terminal of the power transmission circuit. A second terminal of the first transmission transistor is coupled to a first node. A control terminal of the first transmission transistor is coupled to a control node. A first terminal of the second transmission transistor is used as a power output terminal of the power transmission circuit. A second terminal of the second transmission transistor is coupled to the first node. When a voltage of the power output terminal is greater than or equal to a voltage of the power input terminal, the first control circuit outputs a first voltage to the control node, to turn off the first transmission transistor and the second transmission transistor.

An example analog signal multiplexer includes two differential input signal ports for receiving a first and a second differential input signals, IN1 and IN2. The multiplexer further includes a differential output signal port with two output terminals OUT+ and OUT, for outputting a signal based on one or more of the input signals IN1 and IN2. Furthermore, the multiplexer includes a pair of load elements, and an additional differential output signal port that has two output terminals TERM+ and TERM. The load elements are not coupled directly to the output terminals OUT+ and OUT, but, rather, are coupled to the output terminals of the additional output signal port, TERM+ and TERM, enabling a modular approach where multiple instances of the multiplexer may be combined on an as-needed basis to realize multiplexing between a larger number of differential inputs that a single multiplexer would allow.

Aspects of the disclosure provide for a circuit. In some examples, the circuit includes a first inverter coupled between first and second nodes, a second inverter coupled between third and fourth nodes, and a first logic circuit having a first input coupled to the second node, a second input coupled to the fourth node, and an output, a first positive feedback circuit coupled between the first and third nodes and having a control input. The first positive feedback circuit comprises a first switch coupled between the first and fifth nodes and having a control input, a second switch coupled between the third and sixth nodes and having a control input, a third inverter having an input coupled to the sixth node and an output coupled to the fifth node, and a fourth inverter having an input coupled to the fifth node and an output coupled to the sixth node.

A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.