Embodiments herein may present an integrated circuit including a switch, where the switch together with other switches forms a network of switches to perform a sequence of operations according to a structure of a collective tree. The switch includes a first number of input ports, a second number of output ports, a configurable crossbar to selectively couple the first number of input ports to the second number of output ports, and a computation engine coupled to the first number of input ports, the second number of output ports, and the crossbar. The computation engine of the switch performs an operation corresponding to an operation represented by a node of the collective tree. The switch further includes one or more registers to selectively configure the first number of input ports and the configurable crossbar. Other embodiments may be described and/or claimed.

Disclosed is a switching device for facilitating data communication between at least one initiator device and multiple target devices. The switching device includes at least one input port configured to receive data from the at least one initiator device. The at least one input port is communicatively coupled to at least one internal bus corresponding to the at least one initiator device. The switching device includes multiple output ports configured to transmit data to the multiple target devices. The multiple output ports are communicatively coupled to a multiple internal bus corresponding to the multiple target devices. The switching device includes at least one routing module communicatively coupled with each of the at least one input port and the multiple output ports. The at least one routing module is configured to route data from the at least one input port to at least one output port of the multiple output ports.

A semiconductor device including a test circuit is miniaturized. The semiconductor device includes r first input terminals (r is an integer of 2 or more), a second input terminal, r functional circuits, a demultiplexer, and a switch circuit. The demultiplexer is a pass transistor logic circuit. R output terminals of the demultiplexer are electrically connected to respective input terminals of the functional circuit and the input terminal is electrically connected to the second input teiminal. Input terminals of the r circuits are electrically connected to the respective first input terminals through the switch circuit. For example, a signal for verification is input to the first input terminal in verification of the functional circuit to operate the demultiplexer. One signal for verification is input to r functional circuits by the demultiplexer.

A switch control circuit includes: a clock generating circuit that generates one or more periodic signals having a predetermined cycle; a clock adjusting circuit that generates one or more control signals by adjusting a bias voltage of the one or more periodic signals and changing an ON period of the one or more periodic signals; and at least one switching circuit including one or more switches that are switched to ON if respective amplitudes of the generated one or more control signals is equal to or higher than a threshold value and that are switched to OFF if the respective amplitudes of the generated one or more control signals is less than the threshold value.

A multi-channel switch device is provided. The multi-channel switch device includes a first-stage switch circuit, at least one second-stage switch circuit, and multiple third-stage switch circuits. The first-stage switch circuit includes a first common-mode node, a first input/output terminal, and at least one first-stage connection terminal. The second-stage switch circuit includes a second common-mode node, a second-stage transmission terminal, and multiple second-stage connection terminals. Each of the third-stage switch circuits includes a third common-mode node, a third-stage transmission terminal, a reference terminal, and a second input/output terminal. Two of the first input/output terminal and the at least one first-stage connection terminal are connected through the first common-mode node. Two of the second-stage transmission terminal and the second-stage connection terminals are connected through the second common-mode node. Two of the third-stage transmission terminal, the reference terminal, and the second input/output terminal are connected through the third common-mode node.

A semiconductor switch includes a plurality of first terminals, a second terminal commonly provided for the plurality of first terminals, a plurality of first MIS switches provided between the plurality of the first terminals and the second terminal, respectively, configured to pass-through or cut-off a high frequency signal between the plurality of the first terminals and the second terminal, and formed on a SOI substrate, and a capacitor formed on the SOI substrate, connected between the second terminal and the plurality of the first MIS switches, and provided for the plurality of the first terminals commonly.

A switching assembly includes a common gate structure. A first transistor includes a first gate terminal. A second transistor includes a second gate terminal. A first coil is electrically connected between the first gate terminal and the common gate structure. A second coil is electrically connected between the second gate terminal and the common gate structure. The first coil and the second coil are inversely inductively coupled with reference to a current supplied through the common gate structure.

An analog front end circuit of an optical pulse energy digitizer includes a multiphase clock circuit, a demultiplexer configured to demultiplex a current pulse stream into demultiplexed current pulse streams, and integrate-and-dump circuits coupled with the demultiplexer. Each ingrate and dump circuit is configured to convert one of the demultiplexed current pulse streams to provide a demultiplexed voltage pulse stream. The multiphase clock circuit includes latches having outputs coupled to a combination logic circuit. The combination logic circuit is configured to provide clock signals for the integrate-and-dump circuits.

A signal generator that provides signals for multiple outputs is presented. In some embodiments, a signal generator can include switching circuitry that is coupled to provide a signal to an active output of a plurality of outputs in response to control signals; a driver that provides the signal to the switching circuitry, the signal being at a frequency appropriate for the active output; and a logic that provides the control signals to the switching circuitry and provides a waveform to the driver, the waveform having the frequency appropriate for the active output, the control signals indicating which of the plurality of outputs is the active output.

A semiconductor switch includes a plurality of first terminals, a second terminal commonly provided for the plurality of first terminals, a plurality of first MIS switches provided between the plurality of the first terminals and the second terminal, respectively, configured to pass-through or cut-off a high frequency signal between the plurality of the first terminals and the second terminal, and formed on a SOI substrate, and a capacitor formed on the SOI substrate, connected between the second terminal and the plurality of the first MIS switches, and provided for the plurality of the first terminals commonly.