Subject matter disclosed herein may relate to correlated electron switches.

Subject matter disclosed herein may relate to correlated electron switches.

In some examples, a device comprises a first driver coupled to a first node, the first node to couple to a first load external to the device. The device comprises a second driver coupled to a second node, the second node coupled to a second load internal to the device. The device comprises a comparison circuit having an inverting input coupled to the first node and a non-inverting input coupled to the second node. Sizes of the second driver and the second load are configured proportionately to sizes of the first driver and the first load, respectively.

The disclosure relates to a switch arrangement for a converter, comprises: a first series connection of at least two switches between two terminals of the switch arrangement, wherein the two switches are semiconductor switches; a second series connection of a first capacitor and a first diode circuit electrically connected in parallel to first part of the first series connection between a first terminal of the two terminals and node between the two switches, wherein the first diode circuit comprises at least one diode; and third series connection of a second capacitor and a second diode circuit electrically connected in parallel to a second part of the first series connection between second terminal of the two terminals and the node between the two switches, wherein the second diode circuit comprises at least one diode. Further a method for switching such a switch arrangement between the conducting state and the non-conducting state.

A gate drive circuit is used in a dynamic characteristic test on a power semiconductor, the gate drive circuit includes a voltage source configured to change a gate voltage of a gate of the power semiconductor, a plurality of resistance setting circuits connected in parallel with the voltage source and the gate, and a switching circuit connecting at least one resistance setting circuit of the resistance setting circuits to the voltage source and the gate.

A FET switch stack has a stacked arrangement of FET switches, a gate resistor network with ladder resistors and common gate resistors, and a gate resistor bypass arrangement. The bypass arrangement has a first set of bypass switches connected across the gate resistors and a second set of bypass switches connected across the ladder resistors. Bypass occurs during at least a portion of the transition state of the stacked arrangement of FET switches.

A method and device for adjusting the switching speed of a MOSFET are disclosed. The MOSFET is connected to drive switch, the collector of the drive switch is connected to the grid of the MOSFET through the grid resistor, the emitter of the drive switch is grounded through the emitter resistor, and the collector of the drive switch is also connected to the source resistor through the collector resistor, the other end of the source resistor is connected to the source of the MOSFET; the drain of the MOSFET is connected to the current source. The method comprises: obtaining the adjustment target of the switching speed for the MOSFET, determining the first resistance value of the emitter resistor and/or the second resistance value of the collector resistor based on said adjustment target, controlling the operation of the MOSFET according to the adjusted resistance value.

The present disclosure provides designs and techniques to improve turn “off” times of a bootstrapped switch, maximizing the total “on” time of the bootstrapped switch. The techniques described herein provide a protection device coupled to the bootstrapped switch. The protection device may be controlled by an input voltage to the bootstrapped switch during a boosting phase and may be controlled by a constant voltage during a non-boosting phase. The techniques for reducing turn “off” times are particularly useful in high-speed applications, such as high-speed, low-voltage analog-to-digital converters.

The present disclosure provides designs and techniques to improve turn “off” times of a bootstrapped switch, maximizing the total “on” time of the bootstrapped switch. The techniques described herein provide a protection device coupled to the bootstrapped switch. The protection device may be controlled by an input voltage to the bootstrapped switch during a boosting phase and may be controlled by a constant voltage during a non-boosting phase. The techniques for reducing turn “off” times are particularly useful in high-speed applications, such as high-speed, low-voltage analog-to-digital converters.

The invention relates to a circuit arrangement (100), comprising a control circuit (104) and a switch element (101) for switching between a first and a second switching state of the switch element (101). The control circuit (104) is designed to provide a variable pre-control voltage dependent on the switching state of the switch element. The pre-control voltage is a voltage that is switched as the control voltage at the switch element (101) during one of the two switching states. The control circuit (104) is also designed to vary the pre-control voltage during each of the switching states.