A system includes a sensor circuit configured to sense a parameter of a power system having an operating voltage greater than a voltage rating of the sensor circuit, an optical communications circuit configured to receive a sensor signal from the sensor circuit and to generate an optical communications signal therefrom, and an optical power supply circuit configured to receive an optical input, to generate electrical power from the received optical input and to supply the generated electrical power to the sensor circuit and the optical communications circuit. A driver circuit may be configured to generate a first control signal applied to a control terminal of the power semiconductor switch, and the optical power supply circuit may be configured to supply the generated electrical power to the sensor circuit, the optical communications circuit and the driver circuit.

A semiconductor device includes a semiconductor layer, a first conductor disposed on the semiconductor layer, a second conductor disposed on the semiconductor layer so as to be separated from the first conductor, a relay portion that is formed on the semiconductor layer so as to straddle the first conductor and the second conductor and that is made of a semiconductor having a first conductivity type region and a second conductivity type region, a first contact by which the first conductivity type region and the second conductivity type region are electrically connected to the first conductor, and a second contact that electrically connects the first conductivity type region of the relay portion and the second conductor together and that is insulated from the second conductivity type region.

A circuit arrangement is provided where the arrangement of a feedback resistor between a first branch and a second branch enables that a voltage is provided at an output terminal in an efficient way, this means with a high settling speed and a low current consumption. The feedback resistor is arranged between a reference node and the output terminal, where the reference node is connected to a current mirror. The circuit arrangement can be employed as a gate driver. Furthermore, a driver block and a method of driving a circuit arrangement are provided.

A gate drive control circuit is provided that charges a gate voltage of a power switch transistor during a power switch transistor on-time period. During a first portion of the on-time period, the gate drive control circuit charges the gate voltage through a relatively-low resistance. During a second portion of the on-time period, the gate drive control circuit charges the gate voltage through a relatively-high resistance. Finally, during a third portion of the on-time period, the gate drive control circuit charges the gate voltage through another relatively-low resistance.

An apparatus for performing level shift control in an electronic device includes an input stage positioned in a level shifter of the electronic device, and an output stage positioned in the level shifter and coupled to the input stage through a set of intermediate nodes. The input stage is arranged for receiving at least one input signal of the level shifter through at least one input terminal of the input stage and controlling voltage levels of the set of intermediate nodes according to the at least one input signal. The input stage includes a hybrid current control circuit coupled to the at least one input terminal and arranged for performing current control for the input stage. The hybrid current control circuit is equipped with multiple sets of parallel paths for controlling currents passing through the set of intermediate nodes, respectively, each set may include two or more paths in parallel.

A switching gate driver and method of operating the gate driver is described. The gate driver includes a first voltage source, and a clamping voltage source configured to have a voltage that is less than that of the first voltage source. There is also a current path, for initial charging of a gate voltage of the switching gate, between the first voltage source and a ground source; and a comparator which is configured to clamp the gate voltage to the clamping voltage source as it approaches the voltage of said clamping voltage source.

An analog switch includes an input terminal, an output terminal, a common gate, and a common source. The switch includes a current source which has a first input coupled to a first voltage supply, a control input coupled to receive a gate boost signal, and an output coupled to the common gate. The current source supplies a boost gate current to the common gate during a boost period and supplies a reduced gate current during a second period different than the boost period. The switch includes a clamp circuit which has a first terminal coupled to the common gate, a second terminal coupled to the common source, and a third terminal. The switch includes a Vgs detection circuit which provides the gate boost signal responsive to a conduction of current through the clamp circuit.

Power switch driver for driving a control terminal of a power switch to drive a load, the power switch driver having a in negative feedback circuit to control current delivered to the control terminal, the negative feedback circuit comprising:—a current output circuit comprising at least one of a current source and a current sink, the current output circuit for providing a said current of a said control terminal and configured to receive an output current control signal to control magnitude of the current provided by the current output circuit;—a terminal voltage input circuit for receiving a voltage from a said control terminal and to output an indication of said voltage;—an amplifier coupled to amplify the terminal voltage indication to generate an amplifier output; and—a reference voltage input circuit for receiving a reference voltage, comprising at least one resistor, the reference voltage input circuit coupled to a charge supply input of the amplifier, wherein—the power switch driver is configured to generate the output current control signal dependent on the amplifier output, and—the power switch driver is configured to reduce the current provided by the current output circuit responsive to an increase in the voltage received by the terminal voltage input circuit.

A vehicle powertrain includes an IGBT and a gate driver. The IGBT is configured to energize an electric machine. The gate driver is configured to apply an off voltage less than a threshold voltage onto a gate of the IGBT while the IGBT is operating in a saturation mode, and in response to expiration of a delay from a transition from saturation to linear mode, apply a voltage pulse above the off voltage to reduce flyback from the electric machine. The gate driver may be configured to, in response to expiration of a delay from a transition from saturation to linear mode, apply a voltage pulse above the off voltage and below the threshold to reduce flyback from the electric machine.

A gate driving circuit of embodiments is provided with a first transistor which controls a gate-on voltage applied to a gate electrode of a switching device, a second transistor which controls a gate-off voltage applied to the gate electrode of the switching device, a driving logic circuit which controls turn-on/turn-off of the first and second transistors, a first power source which supplies the gate-on voltage to the gate electrode when the first transistor is turned on, a second power source which supplies the gate-off voltage to the gate electrode when the second transistor is turned on, a first gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, a second gate resistance variable circuit in which a plurality of field effect transistors is connected in parallel, and a gate resistance control circuit which controls gate voltages of a plurality of field effect transistors.