A galvanically isolated gate driver for a power transistor is disclosed. The gate driver provides various temperature protection features that are enabled by (i) diagnostic circuitry to generate fault signals and monitoring signals, (ii) signal processing to enable communication over a shared communication channel across an isolation barrier, (iii) signal processing to reduce operating current needed for real-time thermal monitoring, and (iv) a disable circuit for unused temperature sensing pins.

A circuit arrangement is disclosed for controlling the switching of a field effect transistor (FET). A current controlled amplifier may be configured to amplify a current in a current sense device to generate an amplified current, wherein the current in the current sense device indicates a current through the FET. A comparator may be coupled to the current sense amplifier to compare a voltage corresponding to the amplified current with a voltage reference and to generate a comparator output based on the comparison, wherein the comparator output controls whether the FET is on or off.

A switch-mode power supply circuit includes a low-side switching transistor, a high-side switching transistor, a low-side current sensing circuit, and a gate driver circuit. The low-side current sensing circuit is coupled to the low-side switching transistor and is configured to sense a current flowing through the low-side switching transistor. The gate driver circuit is coupled to the low-side current sensing circuit and the high-side switching transistor. The gate driver circuit is configured to generate a signal having a first drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being less than a threshold current, and to generate a signal having a second drive strength to switch the high-side switching transistor based on current flowing through the low-side switching transistor being greater than the threshold current. The first drive strength is greater than the second drive strength.

Systems, methods, techniques and apparatuses of a semiconductor control system are disclosed. One exemplary embodiment is a method for protecting a semiconductor switch comprising receiving a first voltage during a second blanking period following a first blanking period; determining whether a short circuit fault is occurring by comparing the first voltage to a fast detection threshold corresponding to a first value of a drain-source voltage of the semiconductor switch; if a short circuit is not occurring: receiving a second voltage after the second blanking period ends; determining whether a short circuit fault is occurring by comparing the second voltage to a slow detection threshold corresponding to a second value of the drain-source voltage; and if a short circuit fault is occurring, opening the semiconductor switch, wherein the first value of the drain-source voltage is greater than the second value of the drain-source voltage.

Systems, methods, techniques and apparatuses of a semiconductor control system are disclosed. One exemplary embodiment is a method for protecting a semiconductor switch comprising receiving a first voltage during a second blanking period following a first blanking period; determining whether a short circuit fault is occurring by comparing the first voltage to a fast detection threshold corresponding to a first value of a drain-source voltage of the semiconductor switch; if a short circuit is not occurring: receiving a second voltage after the second blanking period ends; determining whether a short circuit fault is occurring by comparing the second voltage to a slow detection threshold corresponding to a second value of the drain-source voltage; and if a short circuit fault is occurring, opening the semiconductor switch, wherein the first value of the drain-source voltage is greater than the second value of the drain-source voltage.

An overcurrent protection circuit configured to limit an output current flowing through an output transistor includes a sense transistor that provides a sense current proportional to the output current, a sense resistor through which the sense current flows, a current limiting circuit that detects a sense voltage generated by the sense resistor and controls a gate voltage of the output transistor, and a current correction circuit that provides the sense resistor with a corrected sense current added to the sense current based on a difference of voltage between a drain voltage of the output transistor and a drain voltage of the sense transistor.

An overcurrent protection circuit configured to limit an output current flowing through an output transistor includes a sense transistor that provides a sense current proportional to the output current, a sense resistor through which the sense current flows, a current limiting circuit that detects a sense voltage generated by the sense resistor and controls a gate voltage of the output transistor, and a current correction circuit that provides the sense resistor with a corrected sense current added to the sense current based on a difference of voltage between a drain voltage of the output transistor and a drain voltage of the sense transistor.

An overcurrent protection circuit is provided for a switching element turned on/off based on a control voltage. The overcurrent protection circuit includes a first transistor and a second transistor. The first transistor is a PNP bipolar transistor and has an emitter connected to the control voltage. The second transistor is an NPN bipolar transistor and has a base connected to a collector of the first transistor, a collector connected to a base of the first transistor and pulled up to a predetermined pull-up voltage, and a grounded emitter. When the control voltage exceeds a predetermined first threshold voltage, the first and second transistors are turned on, the control voltage is dropped by drop of the pull-up voltage, and thus the overcurrent protection circuit starts a protection operation of turning off the switching element.

The present disclosure provides techniques for predicting failure of power switches and taking action based on the predictions. In an example, a method can include controlling the at least two parallel-connected power switches via a first driver and a second driver, the first a second driver responsive to a single command signal, measuring a failure characteristic of a first power switch, and disabling a first driver of the first power switch when the first failure characteristic exceeds a failure precursor threshold.

The present disclosure provides techniques for predicting failure of power switches and taking action based on the predictions. In an example, a method can include controlling the at least two parallel-connected power switches via a first driver and a second driver, the first a second driver responsive to a single command signal, measuring a failure characteristic of a first power switch, and disabling a first driver of the first power switch when the first failure characteristic exceeds a failure precursor threshold.