A driver circuit is provided. The driver circuit comprises a power transistor and a gate driver circuit arrangement. The driver circuit is integrated in a package. In addition, the driver circuit comprises a terminal for an external transistor. The external transistor and the power transistor are controlled by the gate driver circuit arrangement in a mutually corresponding manner.

A method for selecting a power source for a load is provided. The method includes monitoring the primary power source, when the primary power source is providing power to the load, determining if a condition of the primary power source crosses a first threshold, when the condition crosses the first threshold, turning on a first power field effect transistor to couple a back-up power source to the load through a second power field effect transistor, when the primary power source is not providing power to the load, determining if a condition of the primary power source crosses a second threshold, and when the condition crosses the second threshold, switching off the first power field effect transistor to couple the primary power source to the load through a third power field effect transistor.

A system includes an output terminal and a linear switch circuit coupled to the output terminal. The linear switch circuit includes a first power field-effect transistor (FET) having: a first channel width; a control terminal; a first current terminal; and a second current terminal, wherein the second current terminal is coupled to the output terminal. The linear switch circuit also includes a second power FET having: a second channel width smaller than the first channel width; a control terminal; a first current terminal coupled to the first current terminal of the first power FET; and a second current terminal coupled to the output terminal. The system also comprises a control circuit coupled to the control terminal of the first power FET and to the control terminal of the second power FET. The control circuit detects a drain-to-source voltage (V.sub.DS) saturation condition and controls the first and second power FETs accordingly.

A method for active gate driving a switching circuit, wherein: a characteristic of a waveform controlled by the switching circuit is represented by a function mapping an input variable to an output metric, and wherein: the input variable comprises: a design variable having a first set of possible values; and an environmental variable having a second set of possible values, wherein the environmental variable is observable but not controllable. The method comprising: performing Bayesian optimisation on the function to generate a model of the function, wherein a next value of the design variable for evaluating the function is selected based on values of an acquisition function associated with a predicted value of the environmental variable; determining a first value of the design variable that optimises the model of the function; and controlling the switching circuit according to the first value of the design variable.

The switch device includes a first circuit. The first circuit has a first end coupled between a first terminal and a second terminal, and the first circuit has the second end coupled between the first terminal and the second terminal or coupled to a third terminal. The first circuit includes a first switch and a second switch. The first switch is coupled between the first end and the second end of the first circuit and is turned on or off according to a first control signal. The second switch is connected to the first switch in parallel and is turned on or off according to a second control signal. The first switch and the second switch include transistors of the same type. In a surge protection mode, the second switch is turned on to dissipate the surge current.

A semiconductor device includes m power transistors (m is an integer of 2 or more) coupled in parallel each of which has a sense source terminal, a Kelvin terminal and a source terminal, a first average circuit that connects the first resistor and the second resistor in order between the sense source terminal and the Kelvin terminal and generates first to fourth average voltages and an arithmetic circuit that measures a first current value flowing through the sense source terminal from the first and second average voltages, measures a second current value flowing through the sense source terminal from the third and fourth average voltages and measures a current value flowing through the source terminal from the first to fourth average voltages and the first and second current values.

For example, a semiconductor device includes an output electrode to be connected to an inductive load, a ground electrode to be connected to a ground terminal, first and second transistors connected in parallel between the output and ground electrodes, an active clamp circuit connected to the gate of the first transistor, and a gate control circuit to control the gates of the first and second transistors to keep the first and second transistors on in a first operation state and off in a second operation state. After a transition from the first operation state to the second, before the active clamp circuit operates, the gate control circuit short-circuits between the gate and source of the second transistor.

The invention relates to a circuit arrangement (200) for controlling a plurality of semiconductor switches connected in parallel, having an activation connection (213) and a deactivation connection (214), and having a plurality of control connections (220), each provided for connection to a control connection (123) of one of the plurality of semiconductor switches, wherein the activation connection (213) and the deactivation connection (214) are each connected to each of the plurality of control connections (220), and wherein a circuit breaker (230) is provided between the activation connection (213) and at least one of the control connections (220), furthermore having at least one detection and control arrangement which is designed to detect a current flow in the at least one of the control connections (220) and, if a short-circuit is detected on the basis of the current flow, to control the circuit breaker (230) to open.

A system may include an output power stage driver comprising a plurality of parallel-coupled field-effect transistors and a current sensor comprising a sense field-effect transistor matched to a matched field-effect transistor of the plurality of parallel-coupled field-effect transistors and gate-coupled and source-coupled to the matched field-effect transistor. The current sensor may be configured to measure a reference voltage across the sense field-effect transistor, measure a sense voltage across the matched field-effect transistor, and determine a current through the output power stage driver based on a comparison of the reference voltage to the sense voltage.

Disclosed herein are switching or other active FET configurations that implement a branch design with one or more interior FETs of a main path coupled in parallel with one or more auxiliary FETs of an auxiliary path. Such designs include a circuit assembly for performing a switching function that includes a branch with a plurality of auxiliary FETs coupled in series and a main FET coupled in parallel with an interior FET of the plurality of auxiliary FETs. The body nodes of the FETs can be interconnected and/or connected to a body bias network. The body nodes of the FETs can be connected to body bias networks to enable individual body bias voltages to be used for individual or groups of FETs.