Multi-semiconductor SSPCs that solve bus level problems affecting systems as well as controller level problems affecting individual multi-semiconductor SSPCs are disclosed. Bus level and controller level problems adversely affect multi-semiconductor SSPCs and their associated systems. The disclosed multi-semiconductor SSPCs solve both bus level and controller level problems by implementing controlled rate-change of voltage (dv/dt) ramp-on rate, to ensure that the voltage on the input bus does not collapse when a multi-semiconductor SSPC is commanded closed and that a minimum amount of power is being dissipated evenly across the switching semiconductors.

A doorbell chime bypass circuit includes a first node, a second node, and a bi-directional FET switch in series with the first node and the second current node. The bi-directional FET switch includes a first FET and a second FET in series, and is configured to cease conducting current between the first and second nodes when gate voltages of the first and second FETs are below a cut-off threshold. The bypass circuit further includes a sensing circuit configured to determine a level of current flowing through the bi-directional FET switch, and a switch controller configured to set the gate voltages of the first and second FETs to a level below the cut-off threshold when the sensing circuit senses that the level of current meets a doorbell press current threshold, causing the bi-directional FET switch to cease conducting current between the first and second nodes.

Disclosed is an electronic circuit. The electronic circuit includes a first transistor device, a second transistor device, and a third transistor device, each having a control node and a load path. The electronic circuit further includes a drive circuit. The load paths of the first and second transistor devices are connected in parallel, the load path of the third transistor device is connected in series with the load paths of the first and second transistor devices, and the first transistor device and the second transistor device are integrated in a common semiconductor body. The drive circuit is configured, based on a control signal, to successively switch on the first transistor device and the second transistor device, so that the second transistor device is switched on when the first transistor device is in an on-state.

A driving device includes a voltage regulator, a voltage generator, and a first NMOSFET. The voltage regulator is coupled between a first high-voltage terminal and the output terminal of the driving device. The voltage regulator receives the first high voltage of the first high-voltage terminal. The voltage regulator steps down the first high voltage to generate a supply voltage. The voltage generator is coupled to a second high-voltage terminal and the output terminal of the driving device. The voltage generator provides a reference voltage for the output terminal of the driving device. The reference voltage is substantially lower than the supply voltage. The first NMOSFET is coupled between the output terminal of the driving device and a low-voltage terminal.

A system on chip (SOC) includes a power distribution network (PDN) that has two different types of power multiplexers. The first power multiplexer type includes a lower resistance switching logic, and the second type includes a higher resistance switching logic as well as digital logic to provide an enable signal to the first type of power multiplexer. A given first-type power multiplexer may have multiple power multiplexers of the second type in a loop, the loop including communication paths for the enable signal and feeding the enable signal back to an enable input of the first-type power multiplexer.

Transistor arrays are disclosed herein. An example transistor array includes a first node for coupling the transistor array to a circuit. A first transistor and a second transistor are coupled to the first node. A gate controller is coupled to the gate of the first transistor and the gate of the second transistor and is for selectively turning on the first transistor and the second transistor. A current source is coupled to the first node and is active when the second transistor is off. Calibration circuitry measures the voltage of the first node when the current source is active.

The present invention relates to a relay driving circuit and a battery system for generating a gate voltage for controlling ON/OFF of a pre-charge relay, and provides a relay driving circuit that controls electrical connection between an external device and a battery pack, including: a transistor that receives a control signal of an enable level to perform an ON operation; a first resistor having a first end connected to a positive electrode of the battery pack and a second end connected to the relay, by the ON operation of the transistor; and a second resistor connected between the the second end of the first resistor and the external device, the relay receives power supplied from the battery pack in a ratio of a resistance value of the second resistor to a sum resistance value of the first resistor and the second resistor to perform an ON operation.

The present invention provides a driving stage circuit, including a driving switch circuit and a conduction resistance adjusting circuit. The driving switch circuit generates an output signal according to a switch control signal. The conduction resistance adjusting circuit clamps the switch control signal to a first clamping level according to a current flowing through the driving switch circuit when the current is higher than a first current threshold, such that the conduction resistance of the driving switch circuit is not smaller than a first resistance so that a short circuit current of the driving switch circuit is not larger than a short circuit current limit, wherein a lowest level of the conduction resistance of the driving switch circuit is smaller than a second resistance and the output voltage level does not exceeds a output voltage limit when the current is lower than the first current threshold.

An electronic circuit for uniform distribution of a current includes: a first MOSFET and a second MOSFET, wherein the first MOSFET and the second MOSFET are connected in parallel in order to distribute a current applied to an input terminal, the current flowing towards an output terminal of the electronic circuit, wherein the input terminal is respectively connected to a drain terminal of the first MOSFET and to a drain terminal of the second MOSFET; and a terminal for a control voltage, wherein the control voltage is applied to a gate terminal of the first MOSFET and to a gate terminal of the second MOSFET. The first MOSFET comprises a first resistor at the gate terminal of the first MOSFET, and the second MOSFET comprises a second resistor at the gate terminal of the second MOSFET.

A switch device includes first and second switch units that are coupled respectively to first and second output terminals. Each of the first and second switch units includes a plurality of diodes and at least one semiconductor-controlled rectifier (SCR), where at least one of the diodes and one of the at least one SCR cooperatively permit a current to flow therethrough to a corresponding one of the first and second output terminals when each thereof operates in an ON state, and where at least one of the diodes and one of the at least one SCR cooperatively permit a current to flow therethrough from a corresponding one of the first and second output terminals when each thereof operates in an ON state.