The disclosure relates to a method and a control device for controlling at power semiconductor switches connected in parallel for switching a total current. The semiconductor switches each have a gate terminal. An input terminal for feeding the total current, an output terminal for discharging the total current, and a joint control terminal for receiving a joint control signal that has the state ‘disconnect’ or ‘connect’ are provided. The power semiconductor switches are each connected between to the input terminal and the output terminal. At least one ascertainment unit is designed to receive the joint control signal, ascertain individual control signals in accordance with the joint control signal to control the individual power semiconductor switches, and output the individual control signals to the gate terminals of the power semiconductor switches. The individual control signals each have the state ‘disconnect’ or ‘connect’ and differ at least temporarily.

A semiconductor device includes a plurality of first transistor cells and a plurality of second transistor cells that are electrically connected in parallel between a collector electrode and an emitter electrode. A gate voltage on each of the plurality of first transistor cells is controlled by a first gate interconnection. A gate voltage on each of the plurality of second transistor cells is controlled by a second gate interconnection. A drive circuit is configured to: apply an ON-voltage of the semiconductor device to each of the first and second gate interconnections when the semiconductor device is turned on; and after a lapse of a predetermined time period since start of application of the ON-voltage, apply an OFF-voltage of the semiconductor device to the second gate interconnection and apply an ON-voltage to the first gate interconnection.

The invention provides a converter and a method for suppressing loop interference of converter. The converter includes first and second switching sets connected to each other. Each switching set includes a plurality of switching devices. The plurality of second switching devices are configured to be turned on for a first time after the turn-off time of the plurality of first switching devices, such that each of the plurality of second switching devices provides a path for current within the first time to reduce a potential difference between the first end of at least one of the plurality of second switching devices and the first end of the remaining of the plurality of second switching devices.

In a general aspect, an apparatus can include a temperature measurement circuit configured to produce a first signal indicating a first operating temperature of a first semiconductor device and a temperature comparison circuit operationally coupled with the temperature measurement circuit. The temperature comparison circuit can be configured to compare the first signal with a second signal indicating a second operating temperature of at least a second semiconductor device and produce a comparison signal indicating whether the indicated first operating temperature is higher, lower or equal to the indicated second operating temperature. The apparatus can also include an adjustment circuit configured to adjust operation of the first semiconductor device based on the comparison signal.

A switching circuit has a primary MOSFET switch connected between first and second terminals that are connected to a power line and a load represented as a resistance and inductance. The primary switch is operable by primary control commands to assume a conductive or non-conductive state. Four protection branches are connected in parallel with the primary switch, each having a series connected resistive element and a secondary MOSFET switch operable by branch control commands received at branch command terminals to assume a conductive or non-conductive state. A timing circuit applies branch turn off control commands in sequence to the branch command terminals, each delayed by a different predetermined time interval relative to when a primary turn off control command is applied to the primary switch.

An integrated circuit is provided with an MCU, which is configured to generate a PWM control signal that is free of switching pattern information therein. A current-estimating gate driver is provided, which is responsive to the PWM signal. This gate driver is configured to drive first and second gate terminals of first and second parallel switching devices (within a hybrid switch) with gate signals that establish a second switching pattern within the hybrid switch. These gate driving operations are performed in response to measuring a first voltage associated with a terminal of the hybrid switch when being driven by gate signals that establish a first switching pattern within the hybrid switch that is different from the second switching pattern. The duty cycles of the gate signals associated with the second switching pattern are unequal and the duty cycles of the gate signals associated with the first switching pattern are unequal.

The invention relates to a method (200) and a control device (1) for controlling at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel for switching a total current (I_ges). The at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel each have a gate terminal for controlling the respective power semiconductor switch (LHS1 . . . LHS2). An input terminal (EA) for feeding the total current (I_ges), an output terminal (AA) for discharging the total current (I_ges) and a joint control terminal (S) for receiving a joint control signal (SI) that has the state ‘disconnect’ or ‘connect’ are provided. The at least two power semiconductor switches (LHS1 . . . LHSn) connected in parallel are connected to the input terminal (EA) at the input end and to the output terminal (AA) at the output end. At least one ascertainment unit (EE) is designed to receive the joint control signal (SI) at the input end, ascertain at least two individual control signals (SI1 . . . SIn) in accordance with the joint control signal (SI) in order to control the at least two power semiconductor switches (LHS1 . . . LHSn), and output the at least two ascertained individual control signals to the gate terminals of the at least two power semiconductor switches at the output end. The at least two individual control signals (SI1 . . . SIn) each have the state ‘disconnect’ or ‘connect’ and differ at least temporarily.

The invention generally relates to methods and circuits for controlling switching of parallel coupled power semiconductor switching devices (3), for example for use in a power converter. In an example, there is provided a circuit for controlling switching of parallel coupled power semiconductor switching devices (3), the circuit comprising: a plurality of drive modules (2), each said module for controlling a said power semiconductor switching device (3); control circuitry to transmit switch command signals to the modules, each said switch command signal to trigger a said drive module to control a said power semiconductor switching device to switch state; and voltage isolation between the drive modules and the control circuitry, wherein each said drive module for controlling a said device comprises: timing circuitry (22) to compare a switching delay of the device and a reference delay, wherein said switching delay is a time interval between detecting a said switching command signal at the drive module and switching of the device in accordance with the detected switching command signal; and delay circuitry (21) to provide a controllable delay to delay a said triggering by a said switching command signal received at the module subsequent to the detected switching command signal, the delay circuitry configured to control the controllable delay according to a result of said comparison of said switching delay of the device, to thereby reduce a time difference between the reference delay and a said switching delay of the device switching in accordance with the subsequent switching command signal.

A method for avoiding parasitic oscillation in a parallel semiconductor switch includes allowing only one of the plurality of power components to control a turn-on transition of the semiconductor switch and allowing only one of the plurality of power components to control a turn-off transition of the semiconductor switch, by setting unbalanced driving impedances for the plurality of power components coupled in parallel. Parasitic oscillation in a switch transition may be avoided without impedance matching, and the switch transition may provide a relatively small impact on switch characteristics.

A semiconductor switching module includes an insulated gate bipolar transistor and a unipolar switching device. The insulated gate bipolar transistor includes a first transistor cell and a supplemental cell, wherein the first transistor cell includes a first gate and a first source and wherein the supplemental cell includes a second gate and a supplemental electrode. The unipolar switching device is based on a wide bandgap material and includes a third gate and a third source. The third gate and the second gate are electrically connected with each other and are disconnected from the first gate. The first source, the supplemental cell and the third source are electrically connected with each other.