A hybrid drive circuit (100, 100) drives a first characteristic transistor and a second characteristic transistor coupled in parallel to the first characteristic transistor according to an input signal (Sin). The hybrid drive circuit (100, 100) includes a first turn-on path (Pc1), a first turn-off path (Ps1), a second turn-on path (Pc2), and a second turn-off path (Ps2). The first turn-on path (Pc1) and the second turn-on path (Pc2) produce a first delay time to delay turning on the first characteristic transistor. The first turn-off path (Ps1) and the second turn-off path (Ps2) produce a second delay time to delay turning off the second characteristic transistor.

An embodiment of a semiconductor device includes a plurality of transistor sections separated from each other and a plurality of diode sections separated from each other. Each transistor section includes an emitter electrode and a collector electrode. Each diode section includes an anode electrode and a cathode electrode. Each transistor section is electrically coupled to a common gate pad. A ratio between an active transistor part and an active diode part of the semiconductor device is adjustable by activating a first number of the transistor sections by selectively contacting the emitter electrodes and the collector electrodes of the first number of transistor sections, and by activating a second number of the diode sections by selectively contacting the anode electrodes and the cathode electrodes of the second number of diode sections.

A driver circuit works to drive a first switch and a second switch connected in parallel to each other. The driver circuit includes first and second charge switches and first and second diodes to turn on only one(s) of the first and second switches selected as an on-target(s). The driver circuit includes first and second individual discharging paths connected to gates of the first and second switches, first and second discharge resistors, a shared discharge path, and a shared discharge resistor. This structure is capable of reducing a switching loss.

Current imbalances between parallel switching devices in a power converter half leg are reduced. A gate driver generates a nominal PWM gate drive signal for a respective half leg. A first feedback loop couples the nominal PWM gate drive signal to a gate terminal of a respective first switching device. The first feedback loop has a first mutual inductance with a current path of a first parallel switching device and has a second mutual inductance with a current path of a second parallel switching device. The first and second mutual inductances are arranged to generate opposing voltages in the first feedback loop, so that when all the parallel switching devices carry equal current then the voltages cancel.

In a power converter, a control circuit has a speed adjustment resistor that limits a control current to adjust a switching speed of each of first and second switching elements. The speed adjustment resistor has a resistance that varies depending on a voltage at the control electrode of each of the first and second switching elements. A feedback route connects between the control electrode of the first switching element and the control electrode of the second switching element. The feedback route has a resistance that is set to be lower than a value of the resistance of the speed adjustment resistor during a predetermined Miller period of each of the first and second switching elements.

In an overcurrent detection circuit for switches parallely connected to each other, sense detectors are respectively provided for the switches. Each of the sense detectors detects a sense voltage of the corresponding one of the switches. The sense voltage of each of the switches is based on a sense current associated with a current flowing through the corresponding one of the switches. A parameter calculator calculates, based on the sense voltages calculated by the respective sense detectors, a determination parameter that is less subject to imbalance between currents flowing through the respective switches. A determiner determines whether a value of the determination parameter is higher than an overcurrent threshold, and determines that there is an overcurrent flowing through at least one of the switches upon determining that the value of the determination parameter is higher than the overcurrent threshold.

A driving device for a semiconductor element includes: a plurality of detection circuits that detect different types of abnormalities of the semiconductor element; a logic circuit that generates an error signal when at least one of the detection circuits detects an abnormality; an alarm signal generating circuit that receives the error signal and generates an alarm signal made of one or a plurality of pulses, the alarm signal having a different pulse width for each of the detection circuits that has detected an abnormality; and a protection operation determining circuit that determines whether or not a protection function of the semiconductor element is operating based on the error signal and the alarm signal, and shuts off input of a drive signal to the semiconductor element when it is determined that the protection function is operating.

A hybrid switch apparatus includes a standard semiconductor switch and a fast semiconductor switch electrically arranged in parallel to form a joint output current path for carrying a load current. The standard switch may be a silicon (Si) MOSFET while the fast switch may be a GaN high electron mobility transistor (HEMT). A means for producing first and second gate drive signals includes a pulse former. The first gate drive signal is applied the standard switch for selectively turning the standard switch on and off. The pulse former outputs the second gate drive signal for driving the fast switch, where the pulse former generates the second gate drive signal as a switch-on pulse starting synchronously with each transition of the first gate drive signal and which generates the second gate drive signal in an OFF state in between pulses to avoid incurring a conduction loss in the fast switch.

Provided is a switch drive circuit that drives a plurality of switches mutually connected in parallel including a charge unit allowing charge current to flow to the gate of the switch; an off switch connecting between the gate of the switch and the ground; a detection unit detecting whether charge state of the gate of the switch is in a predetermined state; and a changeover unit that changes a state of off switches when the charge units allow the charge current to flow to the gate. The changeover unit changes the state of the off switches to be ON when detection units do not detect the charge state of the gate being in the predetermined state, and to change the state of the off switches to be OFF when detection units detect the charge state of the gate being in the predetermined state.

A drive circuit drives switches that are connected to each other in parallel. The drive circuit includes individual discharge paths, a common discharge path, blocking units, a discharge switch, off-holding switches, and a drive control unit. The drive control unit selects, as target switches to be driven to be turned on, at least two switches among the switches. The at least two switches include a first switch and a second switch. The first switch is last to be switched to an off-state among the at least two switches that are selected as the target switches and switched to an on-state. The second switch is other than the first switch among the at least two switches. The off-holding switches includes a first off-holding switch and a second off-holding switch. After switching the second off-holding switch to an on-state, the drive control unit switches the discharge switch to an on-state.