A switch circuit is provided. The switch circuit includes a P-type transistor switch and a first P-type control transistor. The P-type transistor switch includes a first control end, a first output end, and a first input end. The first input end receives a first input signal whose logic level is one. The first P-type control transistor is coupled to the first input end and the first control end. The first P-type control transistor includes a second control end. The second control end receives a second input signal whose logic level is zero to turn on the first P-type control transistor. When the first P-type control transistor is turned on, the first input signal is transmitted to the first control end of the P-type transistor switch to turn off the P-type transistor switch.

In a gate driver for driving a first transistor, the gate driver includes first, second and third push-pull circuits, in each of the push-pull circuits, two transistors are connected in series, an output terminal of the first push-pull circuit is connected to the gate of the first transistor, an output terminal of the second push-pull circuit is connected to the gate of a second transistor included in the first push-pull circuit and an output terminal of the third push-pull circuit is connected to the gate of a third transistor included in the first push-pull circuit.

This document discusses, among other things, apparatus and methods for an edge rate driver for a power converter switch. In an example, the driver can include an input node configured to receive a pulse width modulated signal, a first switch configured to couple a control node of the power converter switch to a supply voltage during a first state, a second switch configured to couple the control node of the power converter switch to a reference voltage during a second state, and a first current source configured to supply charge current to the first switch when the power converter switch transitions from the second state to the first state, the charge current configured to charge a parasitic capacitance of the power converter switch.

Electronic modules, and methods of forming and operating modules, are described. The modules include a capacitor, a first switching device, and a second switching device. The electronic modules further include a substrate such as a DBC substrate, which includes an insulating layer between a first metal layer and a second metal layer, and may include multiple layers of DBC substrates stacked over one another. The first metal layer includes a first portion and a second portion isolated from one another by a trench formed through the first metal layer between the two portions. The first and second switching devices are over the first metal layer, a first terminal of the capacitor is electrically connected to the first portion of the first metal layer, and a second terminal of the capacitor is electrically connected to the second portion of the first metal layer, with the capacitor extending over the trench.

A semiconductor switching string includes a plurality of series-connected semiconductor switching assemblies, each having a main semiconductor switching element that includes first and second connection terminals. The main semiconductor switching element also has an auxiliary semiconductor switching element electrically connected between the first and second connection terminals. Each semiconductor switching assembly also includes a control unit configured to switch on a respective auxiliary semiconductor switching element to selectively create an alternative current path between the first and second connection terminals whereby current is diverted to flow through the alternative current path to reduce the voltage across the corresponding main semiconductor switching element. The or each control unit is further configured to switch on the auxiliary semiconductor switching element when the voltage across the corresponding main semiconductor switching element differs from a voltage reference derived from the voltage across all of the main semiconductor switching elements.

A Radio Frequency (RF) switch having two or more stages coupled in series is disclosed. A first Field-Effect Transistor (FET) with a first control terminal is coupled across a gate resistor to shunt the gate resistor when the first FET is on. An RF switching device is configured to pass an RF signal between a signal input and a signal output when the RF switching device is on. A second FET having a second control terminal coupled to an acceleration output is configured to shunt the RF switching device when the second FET is on. A third FET is coupled between the first control terminal and the signal input for controlling charge on a gate of the first FET. A third control terminal of the third FET is coupled to an acceleration input for controlling an on/off state of the third FET.

Embodiments provide a switching circuit including a transistor and a bias circuit. The transistor may transition between an off state and an on state responsive to a control signal received at a control terminal. The bias circuit may be coupled between the control terminal and a gate terminal of the transistor. The bias circuit may include a gate resistor coupled between the gate terminal and the control terminal. The bias circuit may further include one or more diodes coupled in parallel with the gate resistor between the gate terminal and the control terminal to allow leakage current to pass from the gate terminal through the one or more diodes. In some embodiments, the bias circuit may include a switch coupled with the one or more diodes to selectively couple the one or more diodes in parallel with the gate resistor when the transistor is off.

A sensor output circuit is limited with high accuracy, and reduces radio wave radiation by signal transmission using a single-line signal. The sensor output includes a pulse signal Vin that changes according to a physical quantity to be measured, MOS transistors that perform on/off operations according to the pulse signal Vin, a constant current source that generates a constant current, a MOS transistor which generates a gate voltage of a MOS transistor, MOS transistors which form a current mirror circuit, and the MOS transistor which works to maintain a drain voltage of the MOS transistor at a constant voltage, and the output terminal which is driven by the MOS transistors connected in series. In addition, an output signal from the sensor output circuit is transmitted to a control circuit via an output signal line. The control circuit includes a pull-up resistor, a capacitor, and an input gate circuit.

A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.

Various examples are provided related to supercascode power switches that can be used in, e.g., HV and MV applications. This disclosure introduces a cascaded supercascode (CSC) power switch which can include a series of unit supercascode (USC) circuits; a control switch coupled in series with the series of USC circuits; and an external balancing network coupled to each of the n USC circuits. The series has a plurality of USC circuits, with each of the USC circuits including first and second switches coupled in series and an internal balancing network coupled across the first and second switches. A source of each of the USC circuits is a source of the first switch. The internal balancing network can include a capacitor connected between a gate of the second switch and the source of the first switch and a diode connected in parallel with the capacitor.