A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect and a second interconnect. The first interconnect is on an interconnect level extending in a length direction to connect the PMOS drains together, and the second interconnect is on the interconnect level extending in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level physically couple the first interconnect and the second interconnect to an output of the CMOS device. A third interconnect on the interconnect level extends perpendicular to the length direction and offset from the set of interconnects. The third interconnect is capable of flowing current from the PMOS drains or from the NMOS drains to the output of the CMOS device.

A semiconductor element drive device is provided to solve a problem that because a case of a change in the temperature of the semiconductor element or a current flowing through the semiconductor element is not take into consideration, switching loss and noise cannot be reduced sufficiently. In accordance with input sensing information (temperature T, current I), a timing control unit 3 outputs a delay signal Q to control timing of driving a current increasing circuit 5 so that a reduction of switching loss of an IGBT 101 is maximized. When the IGBT 101 is in turn-on mode or turn-off mode, the current increasing circuit 5 outputs a drive signal in response to the delay signal Q delayed by a given time from output of the drive instruction signal P. In this way, the current increasing circuit 5 increases the current that causes the gate capacitor of the IGBT 101 to be charged/discharged in response to the delay signal Q, thereby increasing a switching speed to reduce switching loss.

A gatedriver circuit for controlling a power electronic switch. The circuit provides a galvanic separation and is magnetically immune. The gatedriver circuit comprises a transformer arranged with two separate cores of magnetically conductive material each forming a closed loop. A first electrical conductor has windings around a part of both cores, and a second electrical conductor also has windings around part of both cores. The two cores are positioned close to each other to allow mutual magnetic interaction. The windings of the first and second electrical conductors around the first core have the same winding direction, and the windings of the first and second electrical conductors around the second core have opposite winding direction of the windings of the first and second electrical conductors around the first core, so as to counteract electric influence induced by a common magnetic field through the closed loops of the first and second cores. Hereby, such gatedriver circuit is suitable for controlling power switches in environments with strong magnetic fields, e.g. inside a high power wind turbine.

A gate voltage control/gate resistance changing circuit (21) is accommodated in the same package (P1) as a switching element (11), and outputs a driving signal to the switching element (11) to control turning on and off of the switching element (11). When an external signal is input from outside of the package (P1) to a terminal (3c) of the package (P1), a changing unit (221) accommodated in the package (P1) changes the switching speed of the switching element (11) based on the signal.

A gate drive circuit of a wide band gap power device (IGBT) includes a buffer, a di/dt sensing network, a turn-on circuit portion and turn-off circuit portion. The buffer, responsive to turn-on, supplies a first current via the first current path to the gate of the IGBT, and responsive to turn-off ceases the supply of the first current. The di/dt sensing network receives a feedback control signal representative of a voltage measurement across a parasitic inductance that exists between a Kelvin emitter and a power emitter of the The turn-on circuit portion, responsive to turn-on and a parasitic inductance of zero volts, supplies a second current via a second current path to the gate of the IGBT. The turn-off circuit portion, responsive to turn-off and a parasitic inductance of zero volts, discharges a gate capacitance of the IGBT through both the first current path and a third current path.

A control circuit includes a detection module configured to detect an operating condition of a semiconductor switching device; a determining module configured to determine a gate allowable voltage of the semiconductor switching device based on the operating condition; and an output module configured to output a control signal to a driving power supply circuit of the semiconductor switching device based on the gate allowable voltage, to control the driving power supply circuit to provide a gate on voltage that is not higher than the gate allowable voltage and that is positively correlated with the gate allowable voltage for the semiconductor switching device. When the operating condition of the semiconductor switching device becomes better, the gate allowable voltage of the semiconductor switching device is increased.

A semiconductor device includes a first switch and a first driver. The first switch selects and outputs one of a power supply potential and a generated potential as a first switch output potential based on a synchronization signal from a transmission circuit and a delayed signal delayed from the synchronization signal. The first driver charges a gate of a bipolar transistor element based on the synchronization signal of the transmission circuit and the first switch output potential.

A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and a control electrode between the semiconductor part and the first electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer and the fifth layer are selectively provided between the first layer and the second electrode. In a method for controlling the semiconductor device, first to third voltages are applied in order to the control electrode while a p-n junction between the first and second layers is biased in a forward direction. The second and third voltages are greater than the first voltage, and the third voltage is less than the second voltage.

A driver circuit for driving a switching device having a control electrode. The driver circuit includes an ON circuit configured to turn on the switching device in response to a first drive signal, and an OFF circuit configured to discharge a parasitic capacitance of the control electrode of the switching device with a constant current, to turn off the switching device, in response to a second drive signal.

A gate drive device for driving a switching element includes: a gate drive circuit that drives a gate of the switching element based on a gate drive signal and a drive performance adjustment signal; a gate voltage detection circuit that outputs an on detection signal or an off detection signal when detecting that a gate voltage of the switching element reaches an on determination set value or an off determination set value; and a control circuit that outputs the drive performance adjustment signal to the gate drive circuit to match a gate drive time with a predetermined gate drive time set value.