A system comprises a gate driver that is configured to couple to a transistor disposed in a transistor module via a first pin. The gate driver comprises a duty cycle measurement circuit having a first input terminal and a first output terminal, the first input terminal coupled to a second pin via an isolator. The duty cycle measurement circuit comprises a flip-flop, a counter, a shift register, and a comparator. The system comprises an analog to digital converter circuit having a second input terminal, a second output terminal, and a reference terminal, the second input terminal coupled to a third pin configured to couple to a temperature-sensitive device disposed in the transistor module, the second output terminal coupled to a fourth pin via the isolator, and the reference terminal coupled to the first output terminal.

A slew rate control circuit is disclosed. The slew rate control circuit includes an input port to receive an input signal, a transmitter to transmit the input signal to an output port and an impedance control circuit coupled between the transmitter and the output port. The impedance control circuit has an adjustable impedance that is configured to be adjusted during a rise and a fall of the input signal using a trim code and an one shot pulse.

A semiconductor device includes first and second electrodes. A first-type layer is between the first and second electrodes. A pair of first gate electrodes is between the first and second electrodes and each is surrounded by a gate insulating film. Second gate electrodes are disposed between the pair of first gate electrodes. A second-type layer is on the first-type layer in a first region between a first gate electrode and one of the second gate electrodes. Another first-type layer is on the second-type layer. This other first-type layer is directly adjacent to the gate insulating film. Another second-type layer is on the other second-type layer. A width of the first-type layer between adjacent second gate electrodes is less than a length of the first-type layer in the region between adjacent second gate electrodes.

The invention relates to a circuit unit for controlling load currents of an electrical load, comprising a circuit logic, at least n switch elements with n≥2, resistance elements with m≥1, wherein the resistance elements can be bridged by means of the switch elements, wherein the circuit logic is designed such that it increases the load current in steps to a final value by means of an activation sequence of the switch elements, and a method for controlling load currents of an electrical load.

A system comprises a gate driver that is configured to couple to a transistor disposed in a transistor module via a first pin. The gate driver comprises a duty cycle measurement circuit having a first input terminal and a first output terminal, the first input terminal coupled to a second pin via an isolator. The duty cycle measurement circuit comprises a flip-flop, a counter, a shift register, and a comparator. The system comprises an analog to digital converter circuit having a second input terminal, a second output terminal, and a reference terminal, the second input terminal coupled to a third pin configured to couple to a temperature-sensitive device disposed in the transistor module, the second output terminal coupled to a fourth pin via the isolator, and the reference terminal coupled to the first output terminal.

The power conversion device includes an inverter circuit in which one or a plurality of current limitation circuits that limit an electric current flowing in each of legs are provided and a control unit that controls, when a target voltage or a target current of the inverter circuit is outside a predetermined range, the current limitation circuits such that the electric current flowing in each of the legs is not limited and alternately performs the ON/OFF control of the two switching elements of each of the legs with a dead time in between and controls, when the target voltage or the target current is within the predetermined range, the current limitation circuits such that the electric current flowing in each of the legs is limited and alternately performs the ON/OFF control the two switching elements of each of the legs of the inverter circuit without the dead time in between.

A drive circuit Dr for a switch that reduces a surge voltage caused when a switch SW is switched to an off state. The drive circuit Dr detects, as an on voltage Von, a collector-emitter voltage of the switch SW while the switch SW is in an on state. When the detected on voltage Von is large, the drive circuit Dr sets a resistance value Rd of a discharging resistor 53 when the switch SW is switched to an off state to be larger than the resistance value Rd when the detected on voltage Von is small. More specifically, the drive circuit Dr sets the resistance value Rd to a larger value as the detected on voltage Von is increased.

A cascode switch comprising a normally-on semiconductor device comprising a gate, a source and a drain, and a normally-off semiconductor device comprising a gate, a source and a drain. The drain of the normally-off semiconductor device coupled to the normally-on semiconductor device, the source of the normally-on semiconductor device coupled to the drain of the normally-off semiconductor device and the gate of the normally-on semiconductor device coupled to the source of the normally-off semiconductor device. The cascode switch further comprises a leakage current clamp coupled across the normally-off semiconductor device, the leakage current clamp circuit configured to prevent the drain of the normally-off semiconductor from going too high due to leakage current.

A load control device for controlling power delivered from an alternating-current power source to an electrical load may comprise a controllably conductive device, a control circuit, and an overcurrent protection circuit that is configured to be disabled when the controllably conductive device is non-conductive. The control circuit may be configured to control the controllably conductive device to be non-conductive at the beginning of each half-cycle of the AC power source and to render the controllably conductive device conductive at a firing time during each half-cycle (e.g., using a forward phase-control dimming technique). The overcurrent protection circuit may be configured to render the controllably conductive device non-conductive in the event of an overcurrent condition in the controllably conductive device. The overcurrent protection circuit may be disabled when the controllably conductive device is non-conductive and enabled after the firing time when the controllably conductive device is rendered conductive during each half-cycle.

-- The present disclosure relates to an IGBT driving circuit and a power conversion device. The IGBT driving circuit includes a driving chip with a first driving signal port (Vo); a driving resistor adjustment circuit connected between the first driving signal port (Vo) and a gate (G) of an IGBT, a driving resistor formed by the driving resistor adjustment circuit being adjustable in size; a peak voltage detection circuit connected to the gate (G) of the IGBT which is conductive to the first driving signal port (Vo), the peak voltage detection circuit being configured to monitor whether a peak voltage occurs when the IGBT is turned off; and a resistor adjustment control circuit connected between the peak voltage detection circuit and the driving resistor adjustment circuit and configured to reduce a resistor formed by the driving resistor adjustment circuit when the peak voltage is monitored when the IGBT is turned off.