A power-on reset circuit 10 has: an enhancement-type PMOS transistor P1 whose source is connected to VDD and whose drain is connected to node VJG; a depletion-type NMOS transistor D1 whose drain is connected to the node VJG; a first resistor portion having resistors R1, R2 that are connected in series, and whose one end is connected to a source of the depletion-type NMOS transistor D1, and whose another end is connected to GND, and at which a region between the resistors R1, R2 is connected to a gate of the enhancement-type PMOS transistor P1; and an inverter whose input is connected to the node VJG, and that outputs a reset signal.

A system is described. The system includes a control transistor, a voltage source, a feedback node connected between a drain of the control transistor and the voltage source, a plurality of resistors connected between the voltage source and ground, and a control node connected to a gate of the control transistor. The resistors include a first series-connected set of resistors associated with the control transistor being biased and a second series-connected set of resistors associated with the control transistor being unbiased. During a startup period, the control node is configured to bias the control transistor to select the first series-connected set of resistors, thereby increasing a voltage level of the voltage source to a boosted VCC voltage. After the startup period, the control node is configured to unbias the control transistor to select the second series-connected set of resistors, thereby decreasing the boosted VCC voltage to a normal VCC voltage.

An integrated circuit, a control method, and a system are provided, to improve reliability of the integrated circuit. The integrated circuit mainly includes a power supply pin (P1), a configuration pin (P4, P5), a switchable pull-up resistor (KR1, KR2), and a control unit (2011). The integrated circuit can provide a control signal for a target chip (202) by using the configuration pin (P4, P5) of the integrated circuit. In the integrated circuit, a first end of the switchable pull-up resistor (KR1, KR2) is connected to the power supply pin (P1), a second end of the switchable pull-up resistor (KR1, KR2) is connected to the configuration pin (P4, P5), and a control end of the switchable pull-up resistor (KR1, KR2) is connected to the control unit (2011). The power supply pin (P1) can receive a power supply voltage of the integrated circuit.

A method for preparing photoactive perovskite materials. The method comprises the step of preparing a germanium halide precursor ink. Preparing a germanium halide precursor ink comprises the steps of: introducing a germanium halide into a vessel, introducing a first solvent to the vessel, and contacting the germanium halide with the first solvent to dissolve the germanium halide. The method further comprises depositing the germanium halide precursor ink onto a substrate, drying the germanium halide precursor ink to form a thin film, annealing the thin film, and rinsing the thin film with a second solvent and a salt.

A power supply circuit portion for supplying power comprises a first power rail, a second power rail, first and second output terminals, an energy storage device connected in parallel with the first and second output terminals; and first and second switching portions. The power supply circuit portion has a first mode in which power is supplied to the first and second output terminals by the first and second power rails, and a second mode in which the first switching portion is arranged such that power is not supplied to the first and second output terminals and the second switching portion is arranged to disconnect the energy storage device from the first power rail.

A power down detection circuit and a semiconductor storage apparatus, which can adjust a power down detection level while suppressing temperature dependence, are provided. The power down detection circuit includes a BGR circuit, a trimming circuit, a resistance division circuit, and a comparator. The BGR circuit generates a reference voltage based on a supply voltage. The trimming circuit adjusts the reference voltage based on a trimming signal to generate a reference voltage for power down detection. The resistance division circuit generates an internal voltage lower than the supply voltage. The comparator detects that the internal voltage is lower than the reference voltage for power down detection and outputs a reset signal.

A semiconductor device includes a hysteresis block configured to generate an output voltage at corresponding disabling enabling voltage levels and a core-voltage-gated (CVG) device configured to receive a core voltage, an input terminal of the hysteresis block is coupled to a control node. The CVG device is configured to alter a control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the disabling voltage level in response to the core voltage being at or below a first trigger level. Additionally, the CVG device is configured to alter the control voltage at the control node so as to cause the output voltage of the hysteresis block to be generated at the enabling voltage level in response to the core voltage being at or above a second trigger level, the second trigger level being above the first trigger level.

A method, system, and related component for detecting properness of a PG pin power-on timing sequence are provided. The method comprises: obtaining a pull-up level of a PG pin of a VR chip (S101); determining a value of a pull-up resistor of the PG pin, as a first resistance, when a current injected into the VR chip by using the pull-up level is equal to a maximum withstand current of the VR chip (S102); obtaining an equivalent resistance to ground when the PG pin is at a low level, and calculating, based on the equivalent resistance to ground, a value of the pull-up resistor of the PG pin, as a second resistance, when an output voltage of the PG pin is equal to a preset interference voltage limit value (S103); and outputting first prompt information when it is determined that an actual resistance of the pull-up resistor is lower than the first resistance or the second resistance (S104). The foregoing solution is applied, to determine whether a power-on timing sequence of PG pins in a VR chip is proper, thereby avoiding an incorrect action of a subsequent circuit.

The present disclosure provides a start-up initialization circuit of motor drive system, including a power amplitude detecting and internal power supply module, a controlled delay module, a waveform shaping module and a power supply judging and adjusting module integrated on a same substrate, configured to detect and manage a voltage change of each node of a drive system in real time to cause a motor drive system to realize a start-up initialization process transit from an off state to a normal working state. The present disclosure finally forms the start-up initialization circuit of motor drive system by integrating the power amplitude detecting and internal power supply module, the controlled delay module, the waveform shaping module and the power supply judging and adjusting module and integrating on a single chip, which greatly ensures the reliability of power on and start-up of the motor drive system.

Embodiments of power-on reset (POR) circuits are described. In one embodiment, a POR circuit includes a primary ladder circuit connected to a supply voltage and configured to generate a reference signal for a reset signal in response to the supply voltage and a secondary ladder circuit connected to the supply voltage and configured to bias the primary ladder circuit in response to the supply voltage.