To provide a hysteresis comparator having a small circuit area and low power consumption. The hysteresis comparator includes a comparator, a switch, a first capacitor, a second capacitor, and a logic circuit. A first terminal of the switch is electrically connected to one of a pair of conductive regions of the first capacitor, one of a pair of conductive regions of the second capacitor, and a first input terminal of the comparator. An output terminal of the comparator is electrically connected to an input terminal of the logic circuit. An output terminal of the logic circuit is electrically connected to the other of the pair of conductive regions of the second capacitor. The logic circuit has a function of generating an inverted signal of a signal input to the input terminal of the logic circuit and outputting the inverted signal to the output terminal of the logic circuit. A reference potential is input to the first input terminal of the comparator and the reference potential is held by the switch. Due to change in the potential of the output terminal of the comparator, the reference potential is changed by capacitive coupling of the second capacitor.

A voltage monitoring circuit includes an initializing circuit that outputs an initialization signal generated by delaying a power supply voltage as much as a first delay time, a switching circuit that outputs a switching signal in response to a reset signal, a voltage detecting circuit that outputs a detection signal based on the power supply voltage and stops an operation in response to the switching signal, and an output circuit that outputs the reset signal based on the initialization signal and the detection signal.

Disclosed is an integrated circuit including a first bias current generating circuit. The first bias current generating circuit includes a first amplifier receiving a reference voltage and a first voltage and amplifying a difference between them to output a first output voltage, a first bias current generator receiving the first output voltage and outputting a first bias current in response to the first output voltage, a variable resistor receiving the first bias current and outputting the first voltage in response to the first bias current and a calibration code, a second bias current generator receiving the first output voltage and outputting a second bias current to a peripheral circuit in response to the first output voltage, and a third bias current generator receiving the first output voltage and outputting a third bias current to an external device through a first pad in response to the first output voltage.

A semiconductor device that outputs a reset signal for controlling a reset operation of a reset target circuit connected to a first power supply and a second power supply having a voltage lower than a voltage of the first power supply, the semiconductor device including: a power supply voltage monitoring circuit connected to the first power supply and the second power supply, the power supply voltage monitoring circuit monitors the voltage of the first power supply, wherein the power supply voltage monitoring circuit includes a first transistor having a first conductive type and a second transistor having a second conductive type different from the first conductive type, and wherein the reset signal is switched when the voltage of the first power supply is equal to or greater than a sum of a threshold voltage of the first transistor, and a threshold voltage of the second transistor.

A startup circuit adapted to be coupled to an input voltage supply and operable to supply an output voltage at an output terminal, the startup circuit including: a first transistor having a first control terminal, a first current terminal and a second current terminal, the first current terminal adapted to be coupled to the input voltage supply and the second current terminal coupled to the output terminal; a precharge circuit having a first terminal, a second terminal and a third terminal, the second terminal adapted to be coupled to the input voltage supply and the third terminal coupled to the first control terminal; a current limiter coupled to the precharge circuit, the first control terminal and the second current terminal; a second transistor having a second control terminal, a third current terminal and a fourth current terminal, the third current terminal coupled to the precharge circuit and the second control terminal adapted to be coupled to a control signal; and a third transistor having a third control terminal, a fifth current terminal and a sixth current terminal, the fifth current terminal coupled to the first control terminal and the third control terminal is adapted to be coupled to the control signal.

A power management circuit includes an inverter circuit and a latch circuit. The inverter circuit is configured to receive a first control signal from an inverter input terminal and generate a second control signal at an inverter output terminal. The first control signal carries power status information of a first supply voltage. The latch circuit has a latch supply terminal, a first latch input terminal and a second latch input terminal. The latch supply terminal is coupled to a second supply voltage becoming ready before the first supply voltage. The first latch input terminal and the second latch input terminal are coupled to the inverter output terminal and the inverter input terminal respectively. The latch circuit is configured to generate a third control signal according to respective signal levels of the first control signal and the second control signal, and accordingly perform power control of an integrated circuit.

An electric vehicle includes: a motor configured to drive a wheel; a smoothing capacitor provided within a power supply circuit that supplies electric power to the motor; a processor configured to perform a discharge process when the electric vehicle crashes, the discharge process discharging the smoothing capacitor by controlling the power supply circuit; a power source connected to each of a plurality of electric loads including the processor via a corresponding fuse; a relay circuit electrically connected between the power source and the processor and configured to be driven to electrically connect between the power source and the processor in response to a relay drive signal outputted from the processor; and a holding circuit configured to temporarily hold the relay circuit in a driven state when the processor quits outputting the relay drive signal.

A power-up signal generation circuit including a pre-power-up signal generation block operates by using a first power supply voltage, and generates a pre-power-up signal when the first power supply voltage becomes higher than a first level, and a second power supply voltage becomes higher than a second level; a level shifting block suitable for pull-down driving a first node when the pre-power-up signal is not in an activated state, and pull-up driving the first node with the second power supply voltage when the pre-power-up signal is in the activated state; a driving block suitable for pull-down driving the first node when the second power supply voltage is lower than the second level; and a power-up signal driving block operates by using the second power supply voltage, and generates a power-up signal through a second node by driving the second node based on a voltage level of the first node.

A POR circuit includes a voltage divider coupleable between a supply voltage and a POR trace, including a first element coupled between the supply voltage and a node, and a second element coupled between the node and the POR trace. A switch is drain to source coupled between the POR trace and a reference voltage. A first decoupling capacitor is coupled between the POR trace and the reference voltage. A second decoupling capacitor is coupled between the node and the reference voltage. ESD protection for an integrated circuit includes charging a node of a voltage divider coupled between a supply voltage and a POR trace to a predetermined percentage of the supply voltage, decoupling high frequency noise with a first decoupling capacitor between the POR trace and a reference voltage, and decoupling low frequency noise with a second decoupling capacitor between the node and the reference voltage.

A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.