A circuit includes a power-on control circuit and a voltage generating circuit. The power-on control circuit is configured to cause a power-on control signal to follow a voltage level of a first supply voltage during a first time period that a voltage level of a second supply voltage is less than a threshold value, and to set the power-on control signal to have a voltage level of a reference voltage during a second time period that the voltage level of the second supply voltage is greater than the threshold value. The voltage generating circuit is configured to generate a voltage signal responsive to the power-on control signal.

A latch-based power-on checker (POC) circuit for mitigating potential problems arising from an improper power-up sequence between different power domains (e.g., core and input/output (I/O)) on a system-on-chip (SoC) integrated circuit (IC). In one example, the core power domain having a first voltage (CX) should power up before the I/O power domain having a second voltage (PX), where PX>CX. If PX ramps up before CX, the POC circuit produces a signal indicating an improper power-up sequence, which causes the I/O pads to be placed in a known state. After CX subsequently ramps up, the POC circuit returns to a passive (LOW) state. If CX should subsequently collapse while PX is still up, the POC circuit remains LOW until PX also collapses.

A delay-time correction circuit delays an input signal for generating a pre-drive signal to a drive unit generating a drive signal. A transition-change sensor senses a transition change in one of a turn-on operation and turn-off operation. A correction-signal generator generates a correction signal in response to the transition change sensed by the transition-change sensor and to the input signal. A delay output unit generates an output signal corresponding to the pre-drive signal by delaying the input signal using the correction signal. The delay output unit delays the output signal that instructs the other of a turn-on operation and turn-off operation, from the input signal, in accordance with a length of a period for the transition change in the one of a turn-on operation and turn-off operation that is performed immediately before the other of a turn-on operation and turn-off operation.

Systems and methods for gate driver with field-adjustable undervoltage lockout (UVLO) are disclosed. A gate driver system comprises a control circuit and a driver circuit. The driver circuit incorporates a field-adjustable UVLO, a control logic, and an inverter. The level of the field-adjustable UVLO is adjustable by an external circuit, which can be a resistor based voltage divider. By setting the UVLO level externally adjustable and by moving a reference ground to the external voltage divider, the gate driver system is able to implement gate control for various load without needing extra ground pin.

A semiconductor apparatus includes a control circuit and a level shifter. The control circuit is configured to output a power control signal for activating a data input/output circuit operated by a first voltage when the first voltage is higher than a first set voltage and a second voltage is higher a second set voltage. The level shifter configured to receive the power control signal and lower operating voltages of devices including a plurality of transistors with a thin gate insulating layer based on the power control signal.

A voltage-glitch detection and protection circuit and method are provided. Generally, circuit includes a voltage-glitch-detection-block (GDB) and a system-reset-block coupled to the GDB to generate a reset-signal to cause devices in a chip including the circuit to be reset when a voltage-glitch in a supply voltage (VDD) is detected. The GDB includes a voltage-glitch-detector coupled to a latch. The voltage-glitch-detector detects the voltage-glitch and generates a PULSE to the system-reset-block and latch. The latch receives the PULSE and generates a PULSE_LATCHED signal to the system-reset-block to ensure the reset-signal is generated no matter a width of the PULSE. In one embodiment, the latch includes a filter and a sample and hold circuit to power the latch, and ensure the PULSE_LATCHED signal is coupled to the system-reset-block when a voltage to the GDB or to the latch drops below a minimum voltage due to the voltage-glitch.

An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time.

An electronic circuit includes a native N-channel Metal-Oxide-Semiconductor (NMOS) transistor and a P-channel Metal-Oxide-Semiconductor (PMOS) transistor. The gates of the native NMOS transistor and the PMOS transistor and the source of the native NMOS transistor are grounded. The drains of the native NMOS transistor and the PMOS transistors are connected to one another and to an output port, and the source of the PMOS transistor is connected to an input voltage.

An integrated circuit with a power-on-reset circuit includes an inverter circuit connected between the first and second supply node, a cascode-connected series of transistors MCn, for n going from 1 to N, connected between the first supply node and the input node of the inverter, and a resistive element connected between the input node of the inverter and the second supply node. The transistors in the cascode-connected series of transistors MCn pull up the input node voltage above a trip point voltage when the voltage between the input node and the first supply node is more than a threshold of the cascode-connected series. A circuit connected between the first and second supply nodes is responsive to a POR pulse output by the inverter.

A power on reset circuit according to the present disclosure includes: a reference voltage generating circuit that generates a reference voltage, and also outputs, as a control voltage, a voltage at a node at which a voltage rise is slower than the reference voltage; a comparison voltage generating circuit that operates in response to the control voltage output from the reference voltage generating circuit, and outputs a comparison voltage depending on a power source voltage; and a comparison circuit that compares the comparison voltage output from the comparison voltage generating circuit to the reference voltage output from the reference voltage generating circuit, and outputs an operation signal while the comparison voltage exceeds the reference voltage.