Methods, systems, and devices for controlling a variable capacitor. One aspect features a variable capacitance device that includes a capacitor, a first transistor, a second transistor, and control circuitry. The control circuitry is configured to adjust an effective capacitance of the capacitor by performing operations including detecting a zero-crossing of an input current at a first time. Switching off the first transistor. Estimating a first delay period for switching the first transistor on when a voltage across the capacitor is zero. Switching on the first transistor after the first delay period from the first time. Detecting a zero-crossing of the input current at a second time. Switching off the second transistor. Estimating a second delay period for switching the second transistor on when a voltage across the capacitor is zero. Switching on the second transistor after the second delay period from the second time.

A gate driving circuit including first through (N)th stages is provided. An (M)th stage of the first through (N)th stages includes a pull-up control part, a pull-up part, a carry holding part, a carry part, and a first pull-down part. The pull-up control part applies a second node signal of a second node to a first node in response to the second node signal. The pull-up part outputs a clock signal as an (M)th gate output signal in response to the first node signal. The carry holding part applies the (M)th gate output signal to the second node in response to the (M)th gate output signal. The carry part outputs the clock signal as an (M)th carry signal in response to the first node signal. The first pull-down part pulls down the (M)th gate output signal to a first off voltage.

A gate driving circuit including first through (N)th stages is provided. An (M)th stage of the first through (N)th stages includes a pull-up control part, a pull-up part, a carry holding part, a carry part, and a first pull-down part. The pull-up control part applies a second node signal of a second node to a first node in response to the second node signal. The pull-up part outputs a clock signal as an (M)th gate output signal in response to the first node signal. The carry holding part applies the (M)th gate output signal to the second node in response to the (M)th gate output signal. The carry part outputs the clock signal as an (M)th carry signal in response to the first node signal. The first pull-down part pulls down the (M)th gate output signal to a first off voltage.

A gate control circuit includes a first pulse generator that outputs a first pulse signal when an input signal changes from a first logical level to a second logical level, a first gate controlling portion that controls a gate voltage of a first transistor based on a first control signal when the input signal is at the second logical level, a second pulse generator that outputs a second pulse signal when the input signal changes from the second logical level to the first logical level, and a second gate controlling portion that controls the gate voltage of the first transistor based on a second control signal when the input signal is at the first logical level. The first gate controlling portion includes a first overcurrent controlling portion that controls a voltage level of the first control signal after an expiration of an output period of the first pulse signal.

A gate control circuit includes a first pulse generator that outputs a first pulse signal when an input signal changes from a first logical level to a second logical level, a first gate controlling portion that controls a gate voltage of a first transistor based on a first control signal when the input signal is at the second logical level, a second pulse generator that outputs a second pulse signal when the input signal changes from the second logical level to the first logical level, and a second gate controlling portion that controls the gate voltage of the first transistor based on a second control signal when the input signal is at the first logical level. The first gate controlling portion includes a first overcurrent controlling portion that controls a voltage level of the first control signal after an expiration of an output period of the first pulse signal.

Embodiments of this application relate to the field of electricity, and disclose a drive circuit. In some embodiments of this application, the drive circuit includes a low-side driver module and a delay module, the delay module is configured to output a delay signal of preset duration to the low-side driver module in a case that a control module is being reset; and the low-side driver module is configured to: according to on the delay signal of preset duration, maintain a first state within the preset duration, the first state being the same as a second state; where the second state is a working state of the low-side driver module before the control module is reset, and the second state includes being on or off. The embodiments can help avoid safety hazards caused by unexpected disconnection of a drive signal of the control module.

Embodiments of this application relate to the field of electricity, and disclose a drive circuit. In some embodiments of this application, the drive circuit includes a low-side driver module and a delay module, the delay module is configured to output a delay signal of preset duration to the low-side driver module in a case that a control module is being reset; and the low-side driver module is configured to: according to on the delay signal of preset duration, maintain a first state within the preset duration, the first state being the same as a second state; where the second state is a working state of the low-side driver module before the control module is reset, and the second state includes being on or off. The embodiments can help avoid safety hazards caused by unexpected disconnection of a drive signal of the control module.

An integrated circuit is provided with an MCU, which is configured to generate a PWM control signal that is free of switching pattern information therein. A current-estimating gate driver is provided, which is responsive to the PWM signal. This gate driver is configured to drive first and second gate terminals of first and second parallel switching devices (within a hybrid switch) with gate signals that establish a second switching pattern within the hybrid switch. These gate driving operations are performed in response to measuring a first voltage associated with a terminal of the hybrid switch when being driven by gate signals that establish a first switching pattern within the hybrid switch that is different from the second switching pattern. The duty cycles of the gate signals associated with the second switching pattern are unequal and the duty cycles of the gate signals associated with the first switching pattern are unequal.

A switch includes an input terminal and an output terminal. The switch also includes a first stack having transistors coupled in series, and a second stack having transistors coupled in series. The first stack and the second stack are connected in parallel with one another.

There is provided a power supply switching circuit including a first control signal output unit that outputs a signal exceeding a predetermined potential using a main power supply as a first control signal when a power supply voltage of the main power supply exceeds a predetermined reference voltage, a second control signal output unit that outputs the signal exceeding the predetermined potential using a standby power supply from a battery as a second control signal when a potential of the first control signal does not exceed the predetermined potential, and a power supply output unit that outputs the main power supply when the first control signal exceeds the predetermined potential and outputs the standby power supply when the second control signal exceeds the predetermined potential.