A switching system can include a main switching device configured to switch a voltage, a gate driver having an output coupled to a drive terminal of the main switching device and configured to deliver a drive signal to the main switching device, and a clamp circuit. The clamp circuit can be coupled to the drive terminal of the main switching device. The clamp circuit can include a logic gate configured to drive a clamp switching device coupled to and configured to clamp a voltage at the drive terminal of the main switching device. A drive signal of the clamp switching device can be substantially complementary to the main switching device drive signal. The logic gate can provide at least a portion of a delay between switching transitions of the main switching device and switching transitions of the clamp switching device.

A semiconductor apparatus includes a first receiver, a second receiver, a first delay line, and a second delay line. The first receiver receives an input signal using a first supply voltage. The first delay line delays an output of the first receiver based on a first delay control signal and a first complementary delay control signal to generate a received signal. The second receiver receives a clock signal using a second supply voltage. The second delay line delays an output of the second receiver based on a second delay control signal and a second complementary delay control signal to generate a received clock signal. Delay amounts of the first and second delay lines are complementarily changed based on the first and second supply voltages.

A semiconductor apparatus includes a first receiver, a second receiver, a first delay line, and a second delay line. The first receiver receives an input signal using a first supply voltage. The first delay line delays an output of the first receiver based on a first delay control signal and a first complementary delay control signal to generate a received signal. The second receiver receives a clock signal using a second supply voltage. The second delay line delays an output of the second receiver based on a second delay control signal and a second complementary delay control signal to generate a received clock signal. Delay amounts of the first and second delay lines are complementarily changed based on the first and second supply voltages.

The present description concerns a method of controlling at least one switch (TH), including: the reception of signals (S3-i) having between one another at least one phase shift representative of a desired state of said at least one switch; the obtaining, from said signals, of a value (S1) representative of the desired state; and the application of the representative value to said at least one switch.

The present description concerns a method of controlling at least one switch (TH), including: the reception of signals (S3-i) having between one another at least one phase shift representative of a desired state of said at least one switch; the obtaining, from said signals, of a value (S1) representative of the desired state; and the application of the representative value to said at least one switch.

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors. A method for controlling charge injection in a switch circuit is disclosed whereby injected charge is generated at resistively-isolated nodes between series coupled switching transistors, and the injected charge is conveyed to at least one node of the switch circuit that is not resistively-isolated.

An interlock circuit comprises a plurality of semiconductor switching units electrically connected or connectable in series in a supply line, a plurality of control units electrically connected to the plurality of semiconductor switching units, and a trigger unit electrically connected to the plurality of control circuits. Each control unit activates or deactivates a corresponding semiconductor switching unit in response to trigger signal received from the trigger unit.

A switch including multiple current branches and slope circuitry. The slope circuitry activates or deactivates the current branches one at a time according to a corresponding one of multiple slope functions in response to a transition of the input signal. Each current branch develops a current so that the output node follows a predetermined voltage-current function. Each slope function is other than a step function and may be linear or non-linear. A slope function may be configured as a current-starved inverter charging or discharging a capacitor with a fixed current. Delay circuitry may be included to delay the inputs or the outputs of the slope circuitry configured as multiple slope control circuits. The slope control circuits may be daisy-chained from first to last to effectuate the delay. Each current branch may include an electronic switch and may further include a resistor to determine the current level.

A switch including multiple current branches and slope circuitry. The slope circuitry activates or deactivates the current branches one at a time according to a corresponding one of multiple slope functions in response to a transition of the input signal. Each current branch develops a current so that the output node follows a predetermined voltage-current function. Each slope function is other than a step function and may be linear or non-linear. A slope function may be configured as a current-starved inverter charging or discharging a capacitor with a fixed current. Delay circuitry may be included to delay the inputs or the outputs of the slope circuitry configured as multiple slope control circuits. The slope control circuits may be daisy-chained from first to last to effectuate the delay. Each current branch may include an electronic switch and may further include a resistor to determine the current level.