Some embodiments may include a nanosecond pulser comprising a plurality of solid state switches; a transformer having a stray inductance, L.sub.s, a stray capacitance, C.sub.s, and a turn ratio n; and a resistor with a resistance, R, in series between the transformer and the switches. In some embodiments, the resonant circuit produces a Q factor according to

[00001]$Q=\frac{1}{R}\sqrt{\frac{L_s}{C_s}},$

and the nanosecond pulser produces an output voltage V.sub.out from an input voltage V.sub.in, according to V.sub.out=QnV.sub.in.

Some embodiments may include a nanosecond pulser comprising a plurality of solid state switches; a transformer having a stray inductance, L.sub.s, a stray capacitance, C.sub.s, and a turn ratio n; and a resistor with a resistance, R, in series between the transformer and the switches. In some embodiments, the resonant circuit produces a Q factor according to

[00001]$Q=\frac{1}{R}\sqrt{\frac{L_s}{C_s}},$

and the nanosecond pulser produces an output voltage V.sub.out from an input voltage V.sub.in, according to V.sub.out=QnV.sub.in.

The switch device includes a first circuit. The first circuit has a first end coupled between a first terminal and a second terminal, and the first circuit has the second end coupled between the first terminal and the second terminal or coupled to a third terminal. The first circuit includes a first switch and a second switch. The first switch is coupled between the first end and the second end of the first circuit and is turned on or off according to a first control signal. The second switch is connected to the first switch in parallel and is turned on or off according to a second control signal. The first switch and the second switch include transistors of the same type. In a surge protection mode, the second switch is turned on to dissipate the surge current.

The switch device includes a first circuit. The first circuit has a first end coupled between a first terminal and a second terminal, and the first circuit has the second end coupled between the first terminal and the second terminal or coupled to a third terminal. The first circuit includes a first switch and a second switch. The first switch is coupled between the first end and the second end of the first circuit and is turned on or off according to a first control signal. The second switch is connected to the first switch in parallel and is turned on or off according to a second control signal. The first switch and the second switch include transistors of the same type. In a surge protection mode, the second switch is turned on to dissipate the surge current.

A bi-directional buffer for applications using in an I2C or SMBUS or other bus systems. The bi-directional buffer has an input terminal to receive an input voltage signal and an output terminal for providing an output voltage signal, and the output voltage signal follows the input voltage signal. The output voltage signal is regulated to have a first bias voltage greater than the input voltage signal by a first operational amplifier, or to have a second bias voltage greater than the input voltage signal by a second operational amplifier, the second bias voltage is smaller than the first bias voltage.

A bi-directional buffer for applications using in an I2C or SMBUS or other bus systems. The bi-directional buffer has an input terminal to receive an input voltage signal and an output terminal for providing an output voltage signal, and the output voltage signal follows the input voltage signal. The output voltage signal is regulated to have a first bias voltage greater than the input voltage signal by a first operational amplifier, or to have a second bias voltage greater than the input voltage signal by a second operational amplifier, the second bias voltage is smaller than the first bias voltage.

Apparatus and methods for providing hot-switching immunity for radio frequency switching circuits are disclosed. A radio frequency switching circuit may include both a mechanical switch and a solid-state switch. The mechanical switch may be configurable to couple an output path of a power amplifier to a subsequent component in its transmission path when in a first mechanical switch state and to decouple the output path of the power amplifier from the subsequent component when in a second mechanical switch state. The solid-state switch may be configurable to operatively decouple the mechanical switch from a radio frequency power source when in a first solid-state switch state but not when in a second solid-state switch state. The solid-state switch may be in the first solid-state switch state during transitions of the mechanical switch between the first and second mechanical switch states.

Apparatus and methods for providing hot-switching immunity for radio frequency switching circuits are disclosed. A radio frequency switching circuit may include both a mechanical switch and a solid-state switch. The mechanical switch may be configurable to couple an output path of a power amplifier to a subsequent component in its transmission path when in a first mechanical switch state and to decouple the output path of the power amplifier from the subsequent component when in a second mechanical switch state. The solid-state switch may be configurable to operatively decouple the mechanical switch from a radio frequency power source when in a first solid-state switch state but not when in a second solid-state switch state. The solid-state switch may be in the first solid-state switch state during transitions of the mechanical switch between the first and second mechanical switch states.

Various embodiments relate to a receiver, including: a first bias circuit configured to bias a first and second transistor based upon an bias enable signal and a receive enable signal; a first node between the first transistor and a third transistor; a second node between the second transistor and a fourth transistor; and a second bias circuit configured to bias the first node and the second node based upon the bias enable signal, wherein the third transistor is connected to a first differential output and the gate of the third transistor is connected to a first differential input, and wherein the fourth transistor is connected to a second differential output and the gate of the fourth transistor is connected to a second differential input.

Various embodiments relate to a receiver, including: a first bias circuit configured to bias a first and second transistor based upon an bias enable signal and a receive enable signal; a first node between the first transistor and a third transistor; a second node between the second transistor and a fourth transistor; and a second bias circuit configured to bias the first node and the second node based upon the bias enable signal, wherein the third transistor is connected to a first differential output and the gate of the third transistor is connected to a first differential input, and wherein the fourth transistor is connected to a second differential output and the gate of the fourth transistor is connected to a second differential input.